公开(公告)号：JP2008177185A

公开(公告)日：2008-07-31

申请号：JP2007006545

申请日：2007-01-16

Applicant: Powertech Technology Inc ,  力成科技股▲ふん▼有限公司

Inventor： FAN WEN-JENG

IPC: H01L21/52 ,  H01L23/12 ,  H01L25/04 ,  H01L25/18

CPC classification number: H01L24/73 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a chip package structure for reducing the problem of stress mismatching during temperature circulation test of board level. SOLUTION: In the chip package structure, the area occupied by a chip adhesive material of a low Young's modulus is increased under chip face-up or face-down so that the surface of a substrate not covered with the chip is also coated with the chip adhesive material, and mismatching thermal stress occurring during temperature circulation test is absorbed by a chip adhesive material of the low Young's modulus. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在板级温度循环测试中减少应力失配问题的芯片封装结构。 解决方案：在芯片封装结构中，在芯片面朝下或面朝下的情况下，低杨氏模量的芯片粘合材料占据的面积增加，使得未被芯片覆盖的衬底的表面也被涂覆 使用芯片粘合剂材料，并且在温度循环试验期间发生的不匹配的热应力被低杨氏模量的芯片粘合材料吸收。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008053614A

公开(公告)日：2008-03-06

申请号：JP2006230567

申请日：2006-08-28

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： FAN WEN-JENG

IPC: H01L23/12

CPC classification number: H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: PROBLEM TO BE SOLVED: To provide a BGA package structure in which fall off of a solder ball can be avoided by enhancing moisture resistance. SOLUTION: The BGA package comprises a chip 210, a substrate 220, a mold seal 230, and a plurality of solder balls 240. The chip 210 is mounted on the substrate 220 and connected electrically therewith, a plurality of ball pads 223 and a solder mask layer 224 are formed on the lower surface 222 of the substrate 220, and a plurality of openings 225 are provided in the solder mask layer 224 in order to expose at least a part of the ball pad 223 group. The mold seal 230 has a main body 231 formed on the upper surface 221 of the substrate 220, and a coating layer 232 formed on the lower surface 222 to cover the solder mask layer 224 substantially. A plurality of ball placing holes 233 are provided on the coating layer 232 oppositely to the solder ball 240 group. Each ball placing hole 233 is larger than the opening 225, and each solder ball 240 is bonded to the ball pad 223 group while being aligned with the opposing ball placing hole 233. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种BGA封装结构，其中可以通过提高耐湿性来避免焊球脱落。 解决方案：BGA封装包括芯片210，基板220，模具密封件230和多个焊球240.芯片210安装在基板220上并与其电连接，多个球垫223 并且在衬底220的下表面222上形成焊料掩模层224，并且在焊料掩模层224中设置多个开口225以暴露至少一部分球垫223组。 模具密封件230具有形成在基板220的上表面221上的主体231和形成在下表面222上以大体覆盖焊料掩模层224的涂层232。 多个球放置孔233设置在与焊料球240组相反的涂层232上。 每个球放置孔233大于开口225，并且每个焊球240与对准的球放置孔233对准而与球垫223组接合。版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008047866A

公开(公告)日：2008-02-28

申请号：JP2007141248

申请日：2007-05-29

Applicant: Powertech Technology Inc ,  力成科技股▲ふん▼有限公司

Inventor： CHEN CHIN-TI

IPC: H01L23/12

CPC classification number: H01L23/13 ,  H01L23/49816 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/83051 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92147 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/00015 ,  H01L2224/05599

Abstract: PROBLEM TO BE SOLVED: To provide a chip package structure and a method for manufacturing it, in which contamination caused by die attachment paste is prevented. SOLUTION: The method includes the steps of: providing a substrate 10 having an aperture therethrough; forming a block element 20 along the periphery of the aperture on a top surface of the substrate 10; forming adhesion element 30 along the periphery of the block element 20; installing a chip 40 securely on the substrate 10 by means of the adhesion element 30 such that the chip 40 covers the aperture and the active surface of the chip 40 faces the aperture, the part of the active surface exposing to the aperture; connecting the active surface of the chip 40 electrically with a bottom surface of the substrate 10 by means of a conductive connection element; and forming a mold compound which covers and seals the device. The block element 20 prevents the adhesion element 30 from overflowing into the conductive connection element on the active surface of the chip and then contaminating it during the adhesion of the chip, and also lowers the level of the adhesion element 30 so as to reduce a probability that particles (EMC filler) damage the active surface of the chip 40. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种芯片封装结构及其制造方法，其中防止由芯片附着膏引起的污染。 解决方案：该方法包括以下步骤：提供具有穿过其中的孔的衬底10; 沿着所述孔的周边在所述基板10的顶表面上形成阻挡元件20; 沿块块元件20的周边形成粘合元件30; 通过粘合元件30将芯片40牢固地安装在基板10上，使得芯片40覆盖孔，并且芯片40的有效表面面向孔，活性表面的部分暴露于孔; 通过导电连接元件将芯片40的有源表面与衬底10的底表面电连接; 并形成覆盖并密封该装置的模具化合物。 阻挡元件20防止粘合元件30溢出到芯片的有源表面上的导电连接元件中，然后在芯片的粘附期间将其污染，并且还降低粘合元件30的水平，从而降低概率 该颗粒（EMC填料）会损坏芯片40的活性表面。版权所有：（C）2008，JPO＆INPIT

公开(公告)号：JP2013077628A

公开(公告)日：2013-04-25

申请号：JP2011215270

申请日：2011-09-29

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： CHANG KAI-KYUN

IPC: H01L25/065 ,  G01R31/28 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L2224/16145

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a multi-chip laminated body which manufactures a multi-chip laminated body using TSV mounting process which allows a continuity inspection of a non-board chip laminated body to be conducted in a conventional inspection apparatus.SOLUTION: Multiple test electrodes 130 and multiple exterior electrodes 131 are formed on a surface of a chip 110 formed by dividing a wafer. The chip 110 is provided with multiple silicon through holes 111 which establish electrical continuity between the external electrodes 131 and the test electrodes 130. Next, a non-board chip laminated body 100 is fixed onto an adhesive tape 252 and a filling seal body 150 is formed on the adhesive tape 252. Then, a tape carrier 250 supporting the adhesive tape 252 is fixed to the interior of a wafer test tray 260. In a continuity inspection, the non-board chip laminated body 100 is mounted in the interior of a wafer inspection apparatus 270 with the adhesive tape 252 adhering thereto, the quality of the conduction of the non-board chip laminated body 100 is determined by multiple probes 271 of the wafer inspection apparatus 270.

Abstract translation: 解决的问题：提供一种使用TSV安装工艺制造多芯片层叠体的多芯片层叠体的制造方法，其使得可以在非导体层叠体中进行导电性的连续性检查 常规检验仪器。 解决方案：在通过分割晶片形成的芯片110的表面上形成多个测试电极130和多个外部电极131。 芯片110设置有多个硅通孔111，其在外部电极131和测试电极130之间建立电连续性。接下来，将非板状芯片层叠体100固定到胶带252上，填充密封体150为 然后，将支撑胶带252的带状载体250固定在晶片测试托盘260的内部。在连续性检查中，非板状芯片层叠体100安装在 粘合胶带252的晶片检查装置270，通过晶片检查装置270的多个探针271确定非板状芯片层叠体100的导通质量。（C）2013，JPO＆INPIT

公开(公告)号：JP2012049502A

公开(公告)日：2012-03-08

申请号：JP2011058864

申请日：2011-03-17

Applicant: Powertech Technology Inc ,  力成科技股▲ふん▼有限公司

Inventor： HAYASHI MASASHI ,  SEO SU-KYOM ,  GUO YU YE ,  JUN XING SU

IPC: H01L23/28

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/495 ,  H01L23/552 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To provide a chip package method.SOLUTION: A manufacturing method of a chip package is provided. In the method, a ground ring is directly or indirectly exposed from a package material to form a conductive thin film which electrically connects with the ground ring. Consequently, an electromagnetic interference (EMI) shield is formed to reduce the electromagnetic interference from the exterior. Further, according to this invention, the conductive thin layer of the package structure can be formed in large amounts. Thus, the complexity of the manufacturing process and cost are reduced.

Abstract translation: 要解决的问题：提供芯片封装方法。 解决方案：提供了一种芯片封装的制造方法。 在该方法中，接地环直接或间接暴露于封装材料以形成与接地环电连接的导电薄膜。 因此，形成电磁干扰（EMI）屏蔽以减少来自外部的电磁干扰。 此外，根据本发明，可以大量形成封装结构的导电薄层。 因此，制造过程和成本的复杂性降低。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2010114401A

公开(公告)日：2010-05-20

申请号：JP2008318106

申请日：2008-12-15

Applicant: Powertech Technology Inc ,  力成科技股▲ふん▼有限公司

Inventor： WANG CHIN-FA

IPC: H01L23/50

CPC classification number: H05K3/222 ,  H01L23/4951 ,  H01L23/49517 ,  H01L23/4952 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48464 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19107 ,  H05K3/202 ,  H05K3/281 ,  H05K2201/10287 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To provide an interconnect structure of a leadframe, and to provide an interconnect method of the leadframe. SOLUTION: The interconnect structure of the leadframe includes a plurality of leads 10 and 10', an insulation thin film 20 disposed on a first surface of some leads, a plurality of openings 22 formed in the insulation film to expose of the first surface of some leads, and at least one conductive element 30 selectively connecting the insulation thin film to the exposed part of the leads electrically. In an interconnect method of the leadframe, the insulation film is used to separate the conductive element from the leadframe so that the leadframe can be easily connected. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供引线框架的互连结构，并提供引线框架的互连方法。 引线框架的互连结构包括多个引线10和10'，设置在一些引线的第一表面上的绝缘薄膜20，形成在绝缘膜中的多个开口22以暴露第一 一些引线的表面，以及至少一个导电元件30选择性地将绝缘薄膜电连接到引线的暴露部分。 在引线框架的互连方法中，绝缘膜用于将导电元件与引线框架分离，使得引线框架可以容易地连接。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2010114388A

公开(公告)日：2010-05-20

申请号：JP2008288083

申请日：2008-11-10

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： LEE CHUANG FA ,  LU ZHAOXIANG ,  QIU ZHENGXIAN

IPC: H01L21/52

CPC classification number: H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To provide a window type semiconductor package which avoids the generation of separation phenomenon at a kind of mold flow inlet. SOLUTION: A semiconductor package mainly includes one substrate 110, one chip having one principal surface to be attached to the substrate, one die attaching layer 140 for adhering the chip to a substrate core layer of the substrate, a plurality of bonding wires, and one mold sealing body. One mold flow inlet exceeding chip dimension is formed on one end of a slot of the substrate. Two or more mold flow obstacles are adhered to the substrate core layer and are positioned on an intersection portion of one edge of a die attaching zone and both side edges of the slot. The obstacles are slightly protruded to both sides of the mold flow inlet. Therefore, impact by mold flow can avoid the generation of separation phenomenon at the mold flow inlet while resisting stress to be applied to the die attaching layer and maintain a die attaching space. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种窗型半导体封装，其避免了在一种模流入口处产生分离现象。 解决方案：半导体封装主要包括一个基板110，一个芯片，其具有一个主表面连接到基板，一个芯片附接层140，用于将芯片粘附到基板的基板芯层，多个接合线 ，和一个模具密封体。 超过芯片尺寸的一个模流入口形成在基板的槽的一端。 两个或更多个模流障碍物粘附到基底芯层上，并且位于管芯附接区的一个边缘和槽的两个侧边缘的交叉部分上。 障碍物稍微突出到模具流入口的两侧。 因此，通过模具流动的冲击可以避免在模具流入口处产生分离现象，同时抵抗施加到模具附着层的应力并保持模具附着空间。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2010016324A

公开(公告)日：2010-01-21

申请号：JP2008209233

申请日：2008-08-15

Applicant: Powertech Technology Inc ,  力成科技股▲ふん▼有限公司

Inventor： FANG LI-CHIH ,  LIU CHUN-HSIEN

IPC: H01L21/301 ,  H01L21/304

CPC classification number: B28D5/0082 ,  B26D9/00 ,  H01L21/67092 ,  H01L21/78 ,  Y10T83/0572

Abstract: PROBLEM TO BE SOLVED: To provide a cutting method of a large-size wafer, and to provide its equipment.
SOLUTION: The number of times for moving a wafer is reduced, thus preventing the wafer during a movement process from being damaged. The wafer is mounted to a working susceptor to execute various processes, and the various processes are completed by moving the working susceptor to a treatment apparatus, or moving the treatment apparatus to the working susceptor.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供大尺寸晶片的切割方法，并提供其设备。

解决方案：移动晶片的次数减少，从而防止在移动过程中的晶片被损坏。 将晶片安装到工作基座上以执行各种处理，并且通过将工作基座移动到处理设备或将处理设备移动到工作基座来完成各种过程。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009272359A

公开(公告)日：2009-11-19

申请号：JP2008119501

申请日：2008-05-01

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： FAN WEN-JENG

IPC: H01L23/12 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L24/32 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor package, wherein the change of movement of circumscribed ball contacts can actualize an effect of increased benefit. SOLUTION: The semiconductor package includes: a substrate 210 having a mounting surface 211 and an exposed surface 212; a die attaching adhesive 220 formed on the mounting surface 211; a chip 230 which is targeted to a die attaching area 213 and is provided on the mounting surface 211 by means of the die attaching adhesive 220; a plurality of first circumscribed ball contacts 240 provided on the exposed surface 212; a plurality of second circumscribed contacts 250 which are provided on the exposed surface 212 and are located away from the center line of the die attaching area 213 as compared with a group of the first circumscribed ball contacts 240; and at least ladder-like groove 214 which is formed on the mounting surface 211, wherein in the ladder-like groove 214, the thickness of the substrate 210 therein gradually becomes small like a ladder toward a direction being far away from the center line of the die attaching area 213 and the die attaching adhesive 220 is put in. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：为了提供一种半导体封装，其中外接滚珠接触件的移动变化可以实现增加效益的效果。 解决方案：半导体封装包括：具有安装表面211和暴露表面212的基板210; 形成在安装面211上的贴片粘接剂220; 芯片230，其靶向模具安装区域213，并通过模具安装粘合剂220设置在安装表面211上; 设置在暴露表面212上的多个第一外接球接点240; 多个第二外接触点250设置在暴露表面212上并且与一组第一外接球接触件240相比位于远离管芯附接区域213的中心线的位置; 并且至少形成在安装面211上的阶梯状的槽214，其中，在梯状槽214中，衬底210的厚度逐渐变得像梯子朝向远离中心线的方向 放置模具安装区域213和模具安装粘合剂220.（C）2010，JPO＆INPIT

公开(公告)号：JP2009246329A

公开(公告)日：2009-10-22

申请号：JP2008147441

申请日：2008-06-04

Applicant: Powertech Technology Inc ,  力成科技股▲ふん▼有限公司

Inventor： CHEN CHIN-TI

IPC: H01L25/065 ,  H01L23/50 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L23/49575 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48249 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor package structure capable of preventing a wire from being swept or short-circuited in packaging, and improving a yield. SOLUTION: This semiconductor package structure includes: a plurality of first inner leads; a plurality of second inner leads; a plurality of first outer leads; a plurality of stacked chips; an encapsulating material; and a plurality of wires. A first protrusion portion 200 is protruded on each first inner lead; a plurality of contact surfaces with height differences are formed; a second protrusion portion is protruded from each second inner lead; thereby the lengths of the wires of the semiconductor package structure connected to the stacked chips, the first inner leads, and the second inner leads can be reduced; and the wire sweep and short-circuiting are prevented in a molding process. In addition, manufacturing methods of a lead frame and the semiconductor package structure are also provided. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供能够防止电线在包装中被扫描或短路的半导体封装结构，并提高产量。 解决方案：该半导体封装结构包括：多个第一内引线; 多个第二内引线; 多个第一外引线; 多个堆叠芯片; 封装材料; 和多条电线。 第一突起部分200突出在每个第一内引线上; 形成具有高差的多个接触面; 第二突出部分从每个第二内引线突出; 从而可以减少连接到堆叠的芯片，第一内部引线和第二内部引线的半导体封装结构的引线的长度; 并且在模制过程中防止了线扫和短路。 此外，还提供了引线框架的制造方法和半导体封装结构。 版权所有（C）2010，JPO＆INPIT