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    METHODS AND APPARATUS FOR SUPPORTING SECONDARY PLATFORM BUNDLES
    41.
    发明申请
    METHODS AND APPARATUS FOR SUPPORTING SECONDARY PLATFORM BUNDLES 审中-公开

    公开(公告)号：WO2022144636A1

    公开(公告)日：2022-07-07

    申请号：PCT/IB2021/061355

    申请日：2021-12-06

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： MASSASCUSA, Sofia ,  FOLLERO, Giulio ,  ALFARANO, Marco

    IPC: G06F8/76 ,  H04W12/30 ,  G06F21/71 ,  H04W8/20

    Abstract: A method includes compiling, by a compiler (305) of a Smart Secure Platform (SSP) supporting a Primary Platform (105) and a Secondary Platform, source code comprising an implementation of an operating system of the Secondary Platform and applications of the Secondary Platform, to produce compiled source code compatible by an operating system of the Primary Platform (105); linking, by the compiler (305), personalization data to the compiled source code to produce a native Secondary Platform Bundle (SPB) compatible with the Primary Platform (105), the personalization data being associated with a subscription of a user of the SSP; and delivering, by the compiler, the native SPB.

    INTEGRATED OPTOELECTRONIC DEVICE WITH WAVEGUIDE AND MANUFACTURING PROCESS THEREOF
    42.
    发明申请
    INTEGRATED OPTOELECTRONIC DEVICE WITH WAVEGUIDE AND MANUFACTURING PROCESS THEREOF 审中-公开

    公开(公告)号：WO2014006570A8

    公开(公告)日：2014-01-09

    申请号：PCT/IB2013/055430

    申请日：2013-07-02

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： PAGANI, Alberto ,  MOTTA, Alessandro ,  LOI, Sara

    IPC: G02B6/12 ,  G02B6/43

    Abstract: An integrated electronic device, delimited by a first surface (S 1 ) and by a second surface (S 2 ) and including: a body (2) made of semiconductor material, formed inside which is at least one optoelectronic component chosen between a detector (30) and an emitter (130); and an optical path (OP), which is at least in part of a guided type and extends between the first surface and the second surface, the optical path traversing the body. The optoelectronic component is optically coupled, through the optical path, to a first portion of free space and a second portion of free space, which are arranged, respectively, above and underneath the first and second surfaces.

    VERTICAL SEMICONDUCTOR DEVICE AND MANUFACTURING PROCESS OF THE SAME
    43.
    发明申请
    VERTICAL SEMICONDUCTOR DEVICE AND MANUFACTURING PROCESS OF THE SAME 审中-公开

    公开(公告)号：WO2013128480A9

    公开(公告)日：2013-09-06

    申请号：PCT/IT2012/000060

    申请日：2012-02-28

    Applicant: STMICROELECTRONICS S.R.L. ,  MURABITO Domenico ,  SAGGIO Mario Giuseppe

    Inventor： MURABITO Domenico ,  SAGGIO Mario Giuseppe

    IPC: H01L29/78 ,  H01L29/739 ,  H01L29/08 ,  H01L21/02 ,  H01L21/336

    Abstract: A vertical-conduction electronic device (100; 150), comprising: a semiconductor wafer (1) including a semiconductor layer (2, 3) having a first side (3a), a first type of conductivity (N), and a first doping level; a first body region (32) and a second body region (34), which have a second type of conductivity (P) and extend in the semiconductor layer (2, 3); an enriched region (12), having the first type of conductivity and a second doping " level higher than the first doping level, which extends in the semiconductor layer facing the first side (3a), between the first and second body regions (32, 34); a dielectric filling region (20), which extends in the semiconductor layer, facing the first side (3a), and completely surrounded by the enriched region (12); and a gate structure (29), which extends on the first side (3a) on the enriched region (12), on the dielectric filling region (20), on part of the first body region (32), and on part of the second body region (34).

    VERTICAL SEMICONDUCTOR DEVICE AND MANUFACTURING PROCESS OF THE SAME
    44.
    发明申请
    VERTICAL SEMICONDUCTOR DEVICE AND MANUFACTURING PROCESS OF THE SAME 审中-公开
    垂直半导体器件及其制造工艺

    公开(公告)号：WO2013128480A1

    公开(公告)日：2013-09-06

    申请号：PCT/IT2012/000060

    申请日：2012-02-28

    Applicant: STMICROELECTRONICS S.R.L. ,  MURABITO Domenico ,  SAGGIO Mario Giuseppe

    Inventor： MURABITO Domenico ,  SAGGIO Mario Giuseppe

    IPC: H01L29/78 ,  H01L29/739 ,  H01L29/08 ,  H01L21/02 ,  H01L21/336

    CPC classification number: H01L29/7802 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66712 ,  H01L29/7395

    Abstract: A vertical-conduction electronic device (100; 150), comprising: a semiconductor wafer (1) including a semiconductor layer (2, 3) having a first side (3a), a first type of conductivity (N), and a first doping level; a first body region (32) and a second body region (34), which have a second type of conductivity (P) and extend in the semiconductor layer (2, 3); an enriched region (12), having the first type of conductivity and a second doping " level higher than the first doping level, which extends in the semiconductor layer facing the first side (3a), between the first and second body regions (32, 34); a dielectric filling region (20), which extends in the semiconductor layer, facing the first side (3a), and completely surrounded by the enriched region (12); and a gate structure (29), which extends on the first side (3a) on the enriched region (12), on the dielectric filling region (20), on part of the first body region (32), and on part of the second body region (34).

    Abstract translation: 一种垂直导电电子器件（100; 150），包括：半导体晶片（1），包括具有第一侧（3a），第一导电类型（N）和第一掺杂的半导体层（2,3） 水平; 具有第二导电类型（P）并在半导体层（2,3）中延伸的第一体区（32）和第二体区（34）; 在所述第一和第二体区域（32,32）之间具有第一类型的导电性和比第一掺杂级别高的第二掺杂的富集区域（12），其在面向第一侧面（3a）的半导体层中延伸， 电介质填充区域（20），其在所述半导体层中延伸，面向所述第一侧面（3a），并且被所述富集区域（12）完全包围;以及栅极结构（29），其在第一 在富集区域（12）上的介电填充区域（20）上，第一体区域（32）的一部分上以及第二体区域（34）的一部分上的侧面（3a）。

    PACKAGED ELECTRONIC DEVICE COMPRISING INTEGRATED ELECTRONIC CIRCUITS HAVING TRANSCEIVING ANTENNAS
    45.
    发明申请
    PACKAGED ELECTRONIC DEVICE COMPRISING INTEGRATED ELECTRONIC CIRCUITS HAVING TRANSCEIVING ANTENNAS 审中-公开
    包含收发天线的集成电子电路的包装电子设备

    公开(公告)号：WO2013128348A2

    公开(公告)日：2013-09-06

    申请号：PCT/IB2013/051422

    申请日：2013-02-21

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： PAGANI, Alberto

    CPC classification number: H01Q1/2283 ,  H01L21/56 ,  H01L23/13 ,  H01L23/48 ,  H01L23/481 ,  H01L23/66 ,  H01L24/24 ,  H01L25/03 ,  H01L25/065 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/73259 ,  H01L2225/06524 ,  H01L2225/06531 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/1011 ,  H01L2225/1047 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

    Abstract: A base (2) carries a first chip (3) and a second chip (4) oriented differently with respect to the base and packaged in a package (6). Each chip integrates an antenna and a magnetic via (13). A magnetic coupling path connects the chips, forming a magnetic circuit that enables transfer of signals and power between the chips (3, 4) even if the magnetic path is interrupted, and is formed by a first stretch (5c) coupled between the first magnetic-coupling element (13) of the first chip and the first magnetic-coupling element (12) of the second chip, and a second stretch (5f) coupled between the second magnetic-coupling element (12) of the first chip and the second magnetic-coupling element (13) of the second chip. The first stretch has a parallel portion (5c1, 5c3) extending parallel to the faces (2a, 2b) of the base. The first and second stretches have respective transverse portions (5i1, 5i2) extending on the main surfaces of the second chip, transverse to the parallel portion.

    Abstract translation: 基座（2）承载相对于基座不同定向并封装在封装（6）中的第一芯片（3）和第二芯片（4）。 每个芯片集成天线和磁通（13）。 磁耦合路径连接芯片，形成磁路，即使磁路被中断也能够在芯片（3,4）之间传递信号和电力，并且通过耦合在第一磁性体之间的第一拉伸（5c）形成 第一芯片的耦合元件（13）和第二芯片的第一磁耦合元件（12）以及耦合在第一芯片的第二磁耦合元件（12）和第二芯片之间的第二拉伸（5f） 第二芯片的磁耦合元件（13）。 第一拉伸具有平行于基部的表面（2a，2b）延伸的平行部分（5c1,5c3）。 第一和第二延伸部具有横向于平行部分的在第二芯片的主表面上延伸的相应横向部分（5i1,5i2）。

    COUPLING CIRCUIT FOR POWER LINE COMMUNICATIONS
    47.
    发明申请
    COUPLING CIRCUIT FOR POWER LINE COMMUNICATIONS 审中-公开
    用于电力线通信的耦合电路

    公开(公告)号：WO2012085059A1

    公开(公告)日：2012-06-28

    申请号：PCT/EP2011/073554

    申请日：2011-12-21

    Applicant: STMICROELECTRONICS S.R.L. ,  FIORELLI, Riccardo ,  CATALIOTTI, Antonio ,  DI CARA, Dario ,  TINE', Giovanni

    Inventor： FIORELLI, Riccardo ,  CATALIOTTI, Antonio ,  DI CARA, Dario ,  TINE', Giovanni

    IPC: H04B3/56

    CPC classification number: H03H7/004 ,  H04B3/56 ,  H04B2203/5491

    Abstract: A coupling interface couples a transceiver to one or more capacitive voltage dividers of a power transmission system. The coupling interface includes a first signal path including an adjustable inductance configured to form a resonance circuit with a capacitance associated with the one or more capacitive voltage dividers. The coupling interface may include a second signal path including an adjustable inductance configured to form a resonance circuit with the capacitance associated with the one or more capacitive voltage dividers.

    Abstract translation: 耦合接口将收发器耦合到电力传输系统的一个或多个电容性分压器。 耦合接口包括第一信号路径，其包括被配置为形成具有与一个或多个电容分压器相关联的电容的谐振电路的可调整电感。 耦合接口可以包括第二信号路径，其包括被配置成形成具有与一个或多个电容分压器相关联的电容的谐振电路的可调电感。

    RESONANT BIAXIAL ACCELEROMETER STRUCTURE OF THE MICROELECTROMECHANICAL TYPE
    49.
    发明申请
    RESONANT BIAXIAL ACCELEROMETER STRUCTURE OF THE MICROELECTROMECHANICAL TYPE 审中-公开
    微电子类型的谐波双相加速度计结构

    公开(公告)号：WO2012070021A1

    公开(公告)日：2012-05-31

    申请号：PCT/IB2011/055309

    申请日：2011-11-25

    Applicant: STMICROELECTRONICS S.R.L. ,  POLITECNICO DI MILANO ,  COMI, Claudia ,  CORIGLIANO, Alberto ,  SIMONI, Barbara

    Inventor： COMI, Claudia ,  CORIGLIANO, Alberto ,  SIMONI, Barbara

    IPC: G01P15/097 ,  G01P15/18

    CPC classification number: G01P15/097 ,  G01P15/0888 ,  G01P15/18 ,  G01P2015/082

    Abstract: A microelectromechanical detection structure (1; 1') for a MEMS resonant biaxial accelerometer (16) is provided with: an inertial mass (2; 2'), anchored to a substrate (30) by means of elastic elements (8) in such a way as to be suspended above the substrate (30), the elastic elements (8) enabling inertial movements of detection of the inertial mass (2; 2') along a first axis of detection (x) and a second axis of detection (y) that belong to a plane (xy) of main extension of said inertial mass (2; 2'), in response to respective linear external accelerations (a x , a y ); and at least one first resonant element (10a) and one second resonant element (10b), which have a respective longitudinal extension, respectively along the first axis of detection (x) and the second axis of detection (y), and are mechanically coupled to the inertial mass (2; 2') through a respective one of the elastic elements (8) in such a way as to undergo a respective axial stress (N 1 , N 2 ) when the inertial mass moves respectively along the first axis of detection (x) and the second axis of detection (y).

    Abstract translation: 用于MEMS共振双轴加速度计（16）的微机电检测结构（1; 1'）设置有：惯性块（2; 2'），其通过弹性元件（8）锚固到基底（30） 一种悬挂在基板（30）上方的方式，弹性元件（8）使惯性质量（2; 2'）沿着第一检测轴（x）和第二检测轴线 y），其响应于相应的线性外部加速度（ax，ay）属于所述惯性质量（2; 2'）的主延伸的平面（xy）; 以及至少一个第一谐振元件（10a）和一个第二谐振元件（10b），它们分别具有沿着第一检测轴（x）和第二检测轴（y）的相应的纵向延伸，并且机械耦合 通过所述弹性元件（8）中的相应弹性元件（8）的惯性质量块（2; 2'）以当所述惯性质量分别沿着所述第一检测轴线移动时经受相应的轴向应力（N1，N2） x）和第二检测轴（y）。

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