公开(公告)号：US07643324B2

公开(公告)日：2010-01-05

申请号：US11367507

申请日：2006-03-06

Applicant: Alan Roth

Inventor： Alan Roth

IPC: G11C15/00 ,  G06F13/28

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: A content Addressable memory (CAM) for performing search operations using variable width search data, said CAM comprising a plurality of arrays of CAM cells, each coupled to a respective sub-search data bus, the sub-search buses being confined to form a main search data bus, to which is applied the search data; selector circuits receiving match line signals from respective CAM arrays, the match line signals being indicative of the results of a search and comparison formed in the associated CAM array, the selector circuit being responsive to a mode selection signal for selecting one or more of said match line output signals to be switched to a priority encoder and multiple match resolver (PE-MMR), wherein in a first mode the match line output signals are switched to said PE-MMR and in a second mode groups of match line output signals from selected arrays are switched to said PE-MMR.

Abstract translation: 一种用于使用可变宽度搜索数据执行搜索操作的内容可寻址存储器（CAM），所述CAM包括多个CAM单元阵列，每个阵列耦合到相应的子搜索数据总线，所述子搜索总线被限制为形成主 搜索数据总线，应用搜索数据; 接收来自相应CAM阵列的匹配线信号的选择器电路，匹配线信号表示在相关联的CAM阵列中形成的搜索和比较的结果，选择器电路响应于选择一个或多个所述匹配的模式选择信号 线路输出信号被切换到优先编码器和多重匹配解算器（PE-MMR），其中在第一模式中，匹配线输出信号被切换到所述PE-MMR，并且在第二模式中，来自所选择的匹配线输出信号组 阵列被切换到所述PE-MMR。

公开(公告)号：US20090237966A1

公开(公告)日：2009-09-24

申请号：US12197790

申请日：2008-08-25

Applicant: Eric Soenen ,  Alan Roth ,  Martin Kinyua ,  Justin Shi

Inventor： Eric Soenen ,  Alan Roth ,  Martin Kinyua ,  Justin Shi

IPC: H02M3/00

CPC classification number: H02M3/1588 ,  H02M2001/0012 ,  Y02B70/1466

Abstract: A system and method for controlling a power converter is presented. An embodiment comprises an analog differential circuit connected to an analog-to-digital converter, and comparing the digital error signal to at least a first threshold value. If the digital error signal is less than the first threshold value, a pulse is generated to control the power converter. Another embodiment includes multiple thresholds that may be compared against the digital error signal.

Abstract translation: 提出了一种用于控制功率转换器的系统和方法。 实施例包括连接到模拟 - 数字转换器的模拟差分电路，并将数字误差信号与至少第一阈值进行比较。 如果数字误差信号小于第一阈值，则产生脉冲以控制功率转换器。 另一实施例包括可与数字误差信号进行比较的多个阈值。

公开(公告)号：US20090237959A1

公开(公告)日：2009-09-24

申请号：US12134930

申请日：2008-06-06

Applicant: Eric Soenen ,  Alan Roth ,  Justin Shi ,  Martin Kinyua

Inventor： Eric Soenen ,  Alan Roth ,  Justin Shi ,  Martin Kinyua

IPC: H02M7/00

CPC classification number: H02M3/1588 ,  H02M2001/0012 ,  Y02B70/1466

Abstract: A system and method for controlling a power converter is presented. An embodiment comprises an analog differential circuit connected to an analog-to-digital converter, a digital pulse generator, and a pre-driver to control the power converter. Another embodiment also includes a digital filter as part of the control loop that may be used to control the loop characteristics of the control circuit. Yet another embodiment replaces the differential circuit with a sigma-delta analog-to-digital modulator and a decimator.

Abstract translation: 提出了一种用于控制功率转换器的系统和方法。 实施例包括连接到模拟 - 数字转换器的模拟差分电路，数字脉冲发生器和用于控制功率转换器的预驱动器。 另一实施例还包括作为可用于控制控制电路的环路特性的控制环路的一部分的数字滤波器。 另一个实施例用Σ-Δ模数转换器和抽取器代替了差分电路。

公开(公告)号：US07350137B2

公开(公告)日：2008-03-25

申请号：US11313661

申请日：2005-12-22

Applicant: Richard Foss ,  Alan Roth

Inventor： Richard Foss ,  Alan Roth

IPC: G11C29/00

CPC classification number: G06F11/1064 ,  G11C15/00

Abstract: A method and circuit is provided for detecting and correcting errors in an array of content addressable memory (CAM) cells. The array includes wordlines, searchlines, bitlines, and matchlines for reading from, writing to, and searching CAM cells in the array. The method includes the following steps: a row parity bit corresponding to a parity of a first plurality of bits stored along a row of CAM cells is stored; a column parity bit corresponding to the parity of a second plurality of bits stored along a column of CAM cells is stored; a parity of the first plurality of bits is read and generated and the generated parity is compared to the stored row parity bit, if the generated and stored parity bits do not match, columns of the array are cycled through; a parity of the second plurality of bits is read and generated and the generated parity is compared to the stored column parity bit until a mismatch is indicated; and, a bit located at an intersection of the mismatched row and column is inverted if the mismatch is indicated.

Abstract translation: 提供了一种用于检测和校正内容可寻址存储器（CAM）单元阵列中的错误的方法和电路。 阵列包括用于从阵列中读取，写入和搜索CAM单元的字线，搜索线，位线和匹配线。 该方法包括以下步骤：存储对应于沿着一组CAM单元存储的第一多个比特的奇偶校验位的行奇偶校验位; 存储与沿着CAM单元的列存储的第二多个比特的奇偶校验相对应的列奇偶校验位; 读出并产生第一多个比特的奇偶校验，并且如果生成和存储的奇偶校验位不匹配，则将生成的奇偶校验与存储的行奇偶校验位进行比较，则阵列的列循环; 读取并生成第二多个比特的奇偶校验，并将生成的奇偶校验与存储的列奇偶校验位进行比较，直到指示不匹配为止; 并且如果指示不匹配，位于错配的行和列的交点处的位被反转。

公开(公告)号：US20070136514A1

公开(公告)日：2007-06-14

申请号：US11673703

申请日：2007-02-12

Applicant: Alan ROTH ,  Sean LORD ,  Robert MCKENZIE ,  Dieter HAERLE ,  Steven SMITH

Inventor： Alan ROTH ,  Sean LORD ,  Robert MCKENZIE ,  Dieter HAERLE ,  Steven SMITH

IPC: G06F12/00

CPC classification number: G11C15/00

Abstract: A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical location in the data array block during a CAM search-and-compare operation a register for storing a user defined priority value assigned to each PE block and means for evaluating priority values and the address determined by the plurality of PE blocks to select a PE block having the highest priority data entry.

Abstract translation: 一种用于CAM的优先编码器（PE），包括多个PE块，每个PE块都接收与对应的数据阵列块中的数据条目相对应的多个匹配结果，并且用于基于物理上的数据来确定最高优先级数据条目的地址 在CAM搜索与比较操作期间在数据阵列块中的位置存储用于分配给每个PE块的用户定义的优先级值的寄存器以及用于评估优先级值的装置和由多个PE块确定的地址以选择PE块 具有最高优先级的数据输入。

公开(公告)号：US07188211B2

公开(公告)日：2007-03-06

申请号：US10724576

申请日：2003-12-01

Applicant: Alan Roth ,  Sean Lord ,  Robert McKenzie ,  Dieter Haerle ,  Steven Smith

Inventor： Alan Roth ,  Sean Lord ,  Robert McKenzie ,  Dieter Haerle ,  Steven Smith

IPC: G06F12/00 ,  G06F9/00

CPC classification number: G11C15/00

Abstract: A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical location in the data array block during a CAM search-and-compare operation a register for storing a user defined priority value assigned to each PE block and means for evaluating priority values and the address determined by the plurality of PE blocks to select a PE block having the highest priority data entry.

Abstract translation: 一种用于CAM的优先编码器（PE），包括多个PE块，每个PE块都接收与对应的数据阵列块中的数据条目相对应的多个匹配结果，并且用于基于物理上的数据来确定最高优先级数据条目的地址 在CAM搜索与比较操作期间在数据阵列块中的位置存储用于分配给每个PE块的用户定义的优先级值的寄存器以及用于评估优先级值的装置和由多个PE块确定的地址以选择PE块 具有最高优先级的数据输入。

公开(公告)号：US20050052907A1

公开(公告)日：2005-03-10

申请号：US10902687

申请日：2004-07-30

Applicant: Alan Roth

Inventor： Alan Roth

IPC: G11C15/00 ,  G11C11/34

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: A content Addressable memory (CAM) for performing search operations using variable width search data, said CAM comprising a plurality of arrays of CAM cells, each coupled to a respective sub-search data bus, the sub-search buses being confined to form a main search data bus, to which is applied the search data; selector circuits receiving match line signals from respective CAM arrays, the match line signals being indicative of the results of a search and comparison formed in the associated CAM array, the selector circuit being responsive to a mode selection signal for selecting one or more of said match line output signals to be switched to a priority encoder and multiple match resolver (PE-MMR), wherein in a first mode the match line output signals are switched to said PE-MMR and in a second mode groups of match line output signals from selected arrays are switched to said PE-MMR.

Abstract translation: 一种用于使用可变宽度搜索数据执行搜索操作的内容可寻址存储器（CAM），所述CAM包括多个CAM单元阵列，每个阵列耦合到相应的子搜索数据总线，所述子搜索总线被限制为形成主 搜索数据总线，应用搜索数据; 接收来自相应CAM阵列的匹配线信号的选择器电路，匹配线信号表示在相关联的CAM阵列中形成的搜索和比较的结果，选择器电路响应于选择一个或多个所述匹配的模式选择信号 线路输出信号被切换到优先编码器和多重匹配解算器（PE-MMR），其中在第一模式中，匹配线输出信号被切换到所述PE-MMR，并且在第二模式中，来自所选择的匹配线输出信号组 阵列被切换到所述PE-MMR。

公开(公告)号：US20050001744A1

公开(公告)日：2005-01-06

申请号：US10724576

申请日：2003-12-01

Applicant: Alan Roth ,  Sean Lord ,  Robert McKenzie ,  Dieter Haerle ,  Steve Smith

Inventor： Alan Roth ,  Sean Lord ,  Robert McKenzie ,  Dieter Haerle ,  Steve Smith

IPC: G11C15/00 ,  H03M7/00

CPC classification number: G11C15/00

Abstract: A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical location in the data array block during a CAM search-and-compare operation a register for storing a user defined priority value assigned to each PE block and means for evaluating priority values and the address determined by the plurality of PE blocks to select a PE block having the highest priority data entry.

Abstract translation: 一种用于CAM的优先编码器（PE），包括多个PE块，每个PE块都接收与对应的数据阵列块中的数据条目相对应的多个匹配结果，并且用于基于物理上的数据来确定最高优先级数据条目的地址 在CAM搜索与比较操作期间在数据阵列块中的位置存储用于分配给每个PE块的用户定义的优先级值的寄存器以及用于评估优先级值的装置和由多个PE块确定的地址以选择PE块 具有最高优先级的数据输入。

公开(公告)号：US06771525B2

公开(公告)日：2004-08-03

申请号：US10158196

申请日：2002-05-31

Applicant: Alan Roth

Inventor： Alan Roth

IPC: G11C1500

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: A content Addressable memory (CAM) for performing search operations using variable width search data, said CAM comprising a plurality of arrays of CAM cells, each coupled to a respective sub-search data bus, the sub-search buses being confined to form a main search data bus, to which is applied the search data; selector circuits receiving match line signals from respective CAM arrays, the match line signals being indicative of the results of a search and comparison formed in the associated CAM array, the selector circuit being responsive to a mode selection signal for selecting one or more of said match line output signals to be switched to a priority encoder and multiple match resolver (PE-MMR), wherein in a first mode the match line output signals are switched to said PE-MMR and in a second mode groups of match line output signals from selected arrays are switched to said PE-MMR.

Abstract translation: 一种用于使用可变宽度搜索数据执行搜索操作的内容可寻址存储器（CAM），所述CAM包括多个CAM单元阵列，每个阵列耦合到相应的子搜索数据总线，所述子搜索总线被限制为形成主 搜索数据总线，应用搜索数据; 接收来自相应CAM阵列的匹配线信号的选择器电路，匹配线信号表示在相关联的CAM阵列中形成的搜索和比较的结果，选择器电路响应于选择一个或多个所述匹配的模式选择信号 线路输出信号被切换到优先编码器和多重匹配解算器（PE-MMR），其中在第一模式中，匹配线输出信号被切换到所述PE-MMR，并且在第二模式中，来自所选择的匹配线输出信号组 阵列被切换到所述PE-MMR。

公开(公告)号：US06563727B1

公开(公告)日：2003-05-13

申请号：US10208011

申请日：2002-07-31

Applicant: Alan Roth ,  Hamed Ghassemi

Inventor： Alan Roth ,  Hamed Ghassemi

IPC: G11C1500

CPC classification number: G11C15/00

Abstract: A method for reducing the coupling noise in a Content Addressable Memory (CAM), the CAM having a first bitline pair and a second bitline pair, both pairs aligned along a first axis; a first memory cell connected to the first bitline pair and a second memory cell to the second bitline pair; having a first match line and a first word line aligned along a second axis, the first match line and the first word line connecting the first and the second memory cells defining a first row in a first column; having a second row adjacent the first row, the second row comprising a third cell and a fourth cell, the third and fourth cells connecting the first and second bitline pairs and a second word line and a second match line, the method comprising arranging the first memory cell in a first orientation and the second memory cell in a second orientation, wherein the second orientation being a first axis mirror image to the first orientation; segmenting the first and second bitline pairs between the first row and the second row; adding a first twisting structure to the first bitline pair and a second twisting structure to the second bitline pair; arranging the third cell in a third orientation, the third orientation being rotated 180 degrees with respect to the first orientation; and arranging the fourth cell in a fourth orientation, the fourth orientation being rotated 180 degrees with respect to the second orientation.

Abstract translation: 一种用于减少内容可寻址存储器（CAM）中的耦合噪声的方法，所述CAM具有沿着第一轴对准的第一位线对和第二位线对; 连接到第一位线对的第一存储器单元和到第二位线对的第二存储器单元; 具有沿着第二轴对准的第一匹配线和第一字线，所述第一匹配线和所述第一字线连接限定第一列中的第一行的所述第一和第二存储器单元; 具有与第一行相邻的第二行，第二行包括第三单元和第四单元，第三单元和第四单元连接第一和第二位线对以及第二字线和第二匹配线，该方法包括将第一行 存储单元，并且所述第二存储单元处于第二取向，其中所述第二取向是到所述第一取向的第一轴镜像; 分割第一行和第二行之间的第一和第二位线对; 将第一扭转结构添加到所述第一位线对，将第二扭转结构添加到所述第二位线对; 以第三方向布置第三单元，第三取向相对于第一取向旋转180度; 以及将所述第四单元格设置在第四取向中，所述第四取向相对于所述第二取向旋转180度。