Abstract:
A switching network including one or more switching circuits and a control circuit (CCC), the switching circuit including a time division switching element (SR12-SR78) provided with inputs and outputs for data packets and the switching element being controlled by the control circuit (CCC). This switching element is constituted by a closed loop shift register (SR12-SR78) of which all the stages are controlled by a clock signal (f2) provided by the control circuit (CCC) and form a number of shift register portions (SR12-SR78) which are each (SR12) associated to a parallel input (h12) having access to all stages of this portion. A plurality of inputs (R1/2) of the switching element have access to this parallel input (h12) via a multiplexer (MUX12).
Abstract:
57 Telecommunication switching system and priority arrangement used therein. The switching system includes a plurality of control circuits (DPTC/31) which are each common to a plurality of line circuits (SLIC, DSP, TCF, DPTC) and which are connected via respecitve time division multiplex links (TINA/B, TOUTA/B) with two inferface circuits (TCEA/B) themselves coupled with a switching network (SNW). The transmission of line scanning data between the control circuits and the interface circuits occurs in channel (16) of the time division multiplex links. The priority of transmission is determined by the priority device (CLHA/B).
Abstract:
Switched capacitance feedback control circuit and sigma delta modulator, using same, for digitally encoding an analog inputsignal. The control circuit includes input means (IM3) able to sample and algebraically add an analog input signal [x(t)[ and an analog feedback signal (b), means (IM4) to integrate these added signals and to provide an analog output signal [w(t)], an analog-to-digital converter (ADC) providing a digital output signal (z) in response to the analog output signal, and a one-bit digital-to-analog converter (DAC) providing said feedback signal (b) in response to the output signal (z).
Abstract:
Polarity reversal circuit including a differential amplifier (Tl/4) and a signal source able to apply a constant voltage and a gradually varying voltage to respective inputs of the amplifier each via the series connection of the gate-to- source path of a field effecttransistor (NM2/3), the base-emitterfunc- tion of a bipolar transistor (T7/8) and a resistance (R14/18) constituting together with another resistance (R15/19) a voltage divider connected to a temperature independent reference voltage (VREF).
Abstract:
The present invention relates to electronic circuits and signal generator using them. The signal generator is adapted to generate a signal with pulses having sloping edges and includes a generator circuit (BSG) which is adapted to give the signal (BS+) in the time intervals between the pulses such an amplitude with respect to a second signal (BS-) that this amplitude may be detected by a detector circuit (CO) and in response thereto may be limited by a limiting circuit (S4) to a reference value. The electronic circuits include a comparator circuit (CO) and a modulator circuit (MOD).
Abstract:
This process for superposing two positive photoresist layers on a semiconductor device includes the steps of forming a fluorine containing coating on a portion of the first positive resist layer, baking the thus obtained coated portion between 160°C and 250°C and for 10 to 30 minutes without modifying the properties of the first resist layer, and depositing the second positive resist layer on the thus hardened portion.
Abstract:
The present Pulse Code Modulation (PCM) translators include a first translator (COLI) for translating a PCM input word coded according to the A or mu-iaw into a linear PCM output word and a second translator (LIC0) for translating a linear PCM input word into a PCM output word coded according to the A or mu-iaw. The choice of the A-law or mu-law is done by selecting the binary value of a single control bit (A).
Abstract:
The system includes an exchange coupled to each of a plurality of telephone subsets via an exchange terminal unit (ETU), a line (L) and subscriber terminal unit (STU). Each of these units includes a transmitter and a receiver enabling the units to communicate by modulation and demodulation of a carrier wave and in each unit parts of the receiver and the transmitter are integrated on a same chip both chips being identical. The modulator device is used in the transmitter, whilst the demodulator, AGC and ringer devices are used in the receiver.
Abstract:
The flat article stacking and tray loading apparatus includes an inclined support (3) having a displaceable front part (11) so that the front wall of a tray (122) can be brought into abutment with the front end (123) of a stack (127) carried by the support and to be loaded in the tray after a backing plate (83) supporting the stack front end has been removed. It also includes a conveyor able to apply the front portion of each envelope conveyed in a direction making an angle with the above backing plate against this backing plate and a belt arrangement (30, 31) operating on the front portion of each envelope to cant the rear part of the envelope into engagement with a deflector (69) after the front portion has been applied against the backing plate.
Abstract:
A differential mixer (DM) used in a telecommunication radio transmitter operating with a 3 Volt supply and including a silicon bipolar cross-connected pair of differential amplifiers (A; B) for receiving a first input voltage (LO) at a high frequency, a pair of current sources (I1; I2), and a voltage-to-current MOS converter (VIC) for receiving a second input voltage (VIN) at a lower frequency. The converter is adapted to convert the low frequency voltage to a differential current (INN) and is coupled to the junction points of the amplifiers and the current sources. The converter further includes a regulated differential cascode circuit (P1; P2) to which the low frequency input voltage (VIN) is applied via resistors (RI1; RI2) and which is coupled to the supply terminals (VCC; GND) of the mixer via two pairs of constant current sources (PB1, PB2; NB1, NB2) respectively. Preferably, a constant reference voltage terminal (VCC/2) is applied to the gate electrode of the transistors (P1; P2) of the cascode circuit via an operational amplifier (O1; O2).