公开(公告)号：US20120245798A1

公开(公告)日：2012-09-27

申请号：US13430567

申请日：2012-03-26

Applicant: Robert Martin Coats ,  David Robert Pavlik ,  Ramkumar Subramanian ,  David Edwards

Inventor： Robert Martin Coats ,  David Robert Pavlik ,  Ramkumar Subramanian ,  David Edwards

IPC: G08G9/02 ,  G06F7/00

CPC classification number: G01S7/412 ,  G01S13/867 ,  G01S13/87 ,  G01S13/931 ,  G01S15/025 ,  G01S17/023 ,  G01S2013/9332 ,  G01S2013/9353 ,  G01S2013/9364 ,  G01S2013/9367 ,  G01S2013/9389 ,  G08G1/16 ,  G08G1/166 ,  G08G1/167

Abstract: A collision avoidance system for a machine is disclosed including an obstacle detection system configured to detect an obstacle. The collision avoidance system also includes a display configured to provide information to an operator. The collision avoidance system further includes a controller in communication with the obstacle detection system and the display. The controller is configured to control the display to indicate an obstacle detection based on information received from the obstacle detection system and determine a ground speed of the machine. The controller is also configured to determine a distance since the ground speed of the machine was last at a threshold speed and suppress the indication of the obstacle detection based on the distance since the ground speed of the machine was last at the threshold speed.

Abstract translation: 公开了一种用于机器的防撞系统，包括被配置为检测障碍物的障碍物检测系统。 防撞系统还包括被配置为向操作者提供信息的显示器。 防撞系统还包括与障碍物检测系统和显示器通信的控制器。 控制器被配置为基于从障碍物检测系统接收的信息来控制显示器来指示障碍物检测，并确定机器的地面速度。 控制器还被配置为确定机器的地面速度以阈值速度持续的距离，并且基于距机器的地面速度以阈值速度持续的距离来抑制障碍物检测的指示。

公开(公告)号：US07604903B1

公开(公告)日：2009-10-20

申请号：US10768515

申请日：2004-01-30

Applicant: Bhanwar Singh ,  Srikanteswara Dakshina-Murthy ,  Khoi A. Phan ,  Bharath Rangarajan ,  Ramkumar Subramanian

Inventor： Bhanwar Singh ,  Srikanteswara Dakshina-Murthy ,  Khoi A. Phan ,  Bharath Rangarajan ,  Ramkumar Subramanian

IPC: G03F1/00 ,  G03F1/14

CPC classification number: G03F1/50

Abstract: A mask is provided to be used with nanoprint lithography processes to facilitate reproduction of small features required for the production of integrated circuits. A translucent substrate is provided along with one or more three-dimensional features that include one or more vertical sidewalls. An absorbing material is deposited upon one or more of the vertical sidewalls so that light in an incident direction to an upper surface of the substrate will be absorbed by the absorbing material, resulting in light blocking features. One or more horizontal surfaces are formed upon one or more of the three-dimensional features, which allow light rays to exit a lower surface of the substrate unobstructed by the absorbing material.

Abstract translation: 提供掩模以与纳米印刷光刻工艺一起使用，以便于再现生产集成电路所需的小特征。 提供了一个半透明衬底以及包括一个或多个垂直侧壁的一个或多个三维特征。 吸收材料沉积在一个或多个垂直侧壁上，使得在衬底的上表面的入射方向上的光将被吸收材料吸收，导致阻光特征。 一个或多个水平表面形成在三维特征中的一个或多个上，这允许光线离开衬底的下表面而不被吸收材料阻挡。

公开(公告)号：US20090259401A1

公开(公告)日：2009-10-15

申请号：US12081350

申请日：2008-04-15

Applicant: David Edwards ,  David Robert Pavlik ,  Ramkumar Subramanian ,  Robert Martin Coats

Inventor： David Edwards ,  David Robert Pavlik ,  Ramkumar Subramanian ,  Robert Martin Coats

IPC: G08G1/16

CPC classification number: G01S13/931 ,  G01S7/062 ,  G01S13/862 ,  G01S13/865 ,  G01S13/867 ,  G01S13/87 ,  G01S17/023 ,  G01S2013/9332 ,  G01S2013/9353 ,  G01S2013/9364 ,  G01S2013/9367 ,  G01S2013/9389 ,  G08G1/16 ,  G08G1/166 ,  G08G1/167

Abstract: A collision avoidance system for a machine is disclosed. The collision avoidance system has a first obstacle detection system. The first obstacle detection system is configured to detect a first obstacle and generate a corresponding first signal. Additionally, the collision avoidance system has an operator interface. The operator interface has a display configured to communicate visual information to an operator. The operator interface also has an input device configured to receive selections from the operator and generate a corresponding second signal. In addition, the collision avoidance system has a controller. The controller is in communication with the first obstacle detection system and the operator interface. The controller is configured to control the display to provide a first dangerous obstacle warning to the operator, based on the first signal. The controller is also configured to control the display to provide a second dangerous obstacle warning to the operator, based on the first and second signals.

Abstract translation: 公开了一种用于机器的防撞系统。 防撞系统具有第一障碍物检测系统。 第一障碍物检测系统被配置为检测第一障碍物并产生对应的第一信号。 另外，防撞系统具有操作界面。 操作员接口具有被配置为向操作者传达视觉信息的显示器。 操作员界面还具有配置成从操作者接收选择并产生相应的第二信号的输入设备。 另外，防撞系统有一个控制器。 控制器与第一障碍物检测系统和操作员界面通信。 控制器被配置为基于第一信号来控制显示器以向操作者提供第一危险障碍物警告。 控制器还被配置为基于第一和第二信号来控制显示器以向操作者提供第二危险障碍物警告。

公开(公告)号：US07449348B1

公开(公告)日：2008-11-11

申请号：US10858605

申请日：2004-06-02

Applicant: Srikanteswara Dakshina-Murthy ,  Bhanwar Singh ,  Ramkumar Subramanian ,  Khoi A. Phan

Inventor： Srikanteswara Dakshina-Murthy ,  Bhanwar Singh ,  Ramkumar Subramanian ,  Khoi A. Phan

IPC: H01L21/00

CPC classification number: G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  H01L22/12

Abstract: The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate compensating for retrograde feature profiles on an imprint mask. An aspect of the invention generates feedback information that facilitates control of imprint mask feature profile via employing a scatterometry system to detect retrograde feature profiles, and mitigating the retrograde profiles via a spacer etchback procedure.

Abstract translation: 本发明一般涉及光刻系统和方法，更具体地涉及有助于补偿压印掩模上逆行特征轮廓的系统和方法。 本发明的一个方面产生反馈信息，其通过使用散射测量系统来检测逆行特征轮廓，以及通过间隔回蚀程序来缓解逆行轮廓，从而有助于控制压印掩模特征轮廓。

公开(公告)号：US07309659B1

公开(公告)日：2007-12-18

申请号：US11097029

申请日：2005-04-01

Applicant: Ramkumar Subramanian ,  Calvin T. Gabriel ,  Bhanwar Singh

Inventor： Ramkumar Subramanian ,  Calvin T. Gabriel ,  Bhanwar Singh

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/31144 ,  H01L21/0273 ,  H01L21/76802 ,  H01L21/7681 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: The disclosure provides methods to mitigate and/or eliminate problems associated with removal of carbon-based resists from organic low k dielectrics. The methods include forming an organic low k dielectric layer over a semiconductor substrate, forming a capping layer over the organic low k dielectric layer, forming a silicon-containing resist over the capping layer, patterning the silicon-containing resist layer to expose portions of the capping layer and to form a patterned silicon oxide layer, removing the organic low k dielectric layer to form one or more openings, and removing the patterned silicon oxide layer. The silicon-containing resist facilitates efficient patterning of the organic low k-dielectric layers, and thereby increases the performance and cost-effectiveness of semiconductor devices fabricated using organic low k dielectrics.

Abstract translation: 本公开提供了减轻和/或消除与有机低k电介质去除碳基抗蚀剂有关的问题的方法。 所述方法包括在半导体衬底上形成有机低k电介质层，在有机低k电介质层上形成覆盖层，在覆盖层上形成含硅抗蚀剂，图案化含硅抗蚀剂层以暴露部分 并且形成图案化氧化硅层，去除有机低k电介质层以形成一个或多个开口，以及去除图案化的氧化硅层。 含硅抗蚀剂有利于有机低k电介质层的有效构图，从而提高使用有机低k电介质制造的半导体器件的性能和成本效益。

公开(公告)号：US07221060B1

公开(公告)日：2007-05-22

申请号：US11074602

申请日：2005-03-08

Applicant: Bhanwar Singh ,  Khoi A. Phan ,  Bharath Rangarajan ,  Iraj Emami ,  Ramkumar Subramanian

Inventor： Bhanwar Singh ,  Khoi A. Phan ,  Bharath Rangarajan ,  Iraj Emami ,  Ramkumar Subramanian

IPC: H01L23/544

CPC classification number: G03F7/70625 ,  G03F7/70633 ,  G03F9/7076 ,  Y10S438/975

Abstract: Systems and/or methods are disclosed for aligning multiple layers of a multi-layer semiconductor device fabrication process and/or system utilizing a composite alignment mark. A component is provided to form the composite alignment mark, such that a first portion of the composite alignment mark is associated with a layer of the wafer and a second portion of the composite alignment mark is associated with a disparate layer of the wafer. An alignment component is utilized to align a reticle for a layer to be patterned to the composite alignment mark.

Abstract translation: 公开了用于对准多层半导体器件制造工艺和/或利用复合对准标记的系统的多层的系统和/或方法。 提供组件以形成复合对准标记，使得复合对准标记的第一部分与晶片的层相关联，并且复合对准标记的第二部分与晶片的不同层相关联。 使用对准部件将待图案化的层的掩模版对准到复合对准标记。

公开(公告)号：US07109046B1

公开(公告)日：2006-09-19

申请号：US10768514

申请日：2004-01-30

Applicant: Ramkumar Subramanian ,  Bhanwar Singh ,  Khoi A. Phan

Inventor： Ramkumar Subramanian ,  Bhanwar Singh ,  Khoi A. Phan

IPC: H01L21/00

CPC classification number: H01L22/12

Abstract: The present invention relates generally to semiconductor processing, and more particularly to methods and systems for reducing costs of wafer production by analyzing key aspects of wafer status to determine whether to initiate corrective measures to salvage a wafer at an early stage and before substantial costs are incurred in fabricating a defective wafer. One aspect of the present invention provides for growing an oxide layer on a wafer upon a determination that an oxide layer on the wafer surface is absent or is present but inadequate. Another aspect of the present invention provides for a determination of whether to apply preemptory corrective treatment(s) to a wafer surface based on the presence and/or magnitude of nitrogen signatures in an extant oxide surface layer, which can indicate that an undesirable defect known as “footing” will occur during a post-exposure delay period. Thus, the invention advantageously reduces production costs by facilitating a most correct decision to mitigate the source(s) of potential defects at an early stage and, thus, before substantial costs are incurred in production of the wafer.

Abstract translation: 本发明一般涉及半导体处理，更具体地说，涉及通过分析晶片状态的关键方面来降低晶片生产成本的方法和系统，以确定是否启动在早期阶段挽救晶片的纠正措施以及在大量成本产生之前 在制造缺陷晶片时。 本发明的一个方面提供了在确定晶片表面上的氧化物层不存在或存在但不足的情况下，在晶片上生长氧化物层。 本发明的另一方面提供了根据现有氧化物表面层中氮标记的存在和/或大小来确定是否对晶片表面施加抢占式校正处理，其可以指示不期望的缺陷已知 因为在曝光后延迟期间将发生“立足”。 因此，本发明有利地通过促进最正确的决定来降低生产成本，以在早期阶段减轻潜在缺陷的来源，并且因此在生产晶片之前花费大量成本之前。

公开(公告)号：US07076320B1

公开(公告)日：2006-07-11

申请号：US10838827

申请日：2004-05-04

Applicant: Khoi A. Phan ,  Bhanwar Singh ,  Ramkumar Subramanian

Inventor： Khoi A. Phan ,  Bhanwar Singh ,  Ramkumar Subramanian

IPC: G06F19/00

CPC classification number: H01L21/67253 ,  G03F7/70525

Abstract: Systems and methods that improve process control in semiconductor manufacturing are disclosed. According to an aspect of the invention, conditions in a cluster tool environment and/or a wafer therein can be monitored in-situ via, for example, a scatterometry system, to determine whether parameters associated with wafer production are within control limits. A cluster tool environment can include, for example, a lithography track, a stepper, a plasma etcher, a cleaning tool, a chemical bath, etc. If an out-of-control condition is detected, either associated with a tool in the cluster tool environment or with the wafer itself, compensatory measures can be taken to correct the out-of-control condition. The invention can further employ feedback/feed-forward loop(s) to facilitate compensatory action in order to improve process control.

Abstract translation: 公开了改进半导体制造过程控制的系统和方法。 根据本发明的一个方面，可以通过例如散射测量系统原地监测集群工具环境和/或其中的晶片中的条件，以确定与晶片生产相关的参数是否处于控制限度内。 集群工具环境可以包括例如光刻轨迹，步进器，等离子体蚀刻器，清洁工具，化学浴等。如果检测到失控状态，则与集群中的工具相关联 工具环境或晶圆本身，可采取补偿措施来纠正失控状态。 本发明可以进一步采用反馈/前馈回路来促进补偿动作，以改善过程控制。

公开(公告)号：US07064846B1

公开(公告)日：2006-06-20

申请号：US10646190

申请日：2003-08-22

Applicant: Gilles Amblard ,  Bhanwar Singh ,  Khoi A. Phan ,  Ramkumar Subramanian

Inventor： Gilles Amblard ,  Bhanwar Singh ,  Khoi A. Phan ,  Ramkumar Subramanian

IPC: G01B11/04

CPC classification number: G03F7/40

Abstract: The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate the reduction of line-edge roughness (LER) and/or standing wave expression during pattern line formation in an integrated circuit. Systems and methods are disclosed for retaining a target critical dimension (CD) of photoresist lines, comprising a non-lithographic shrink component that facilitates mitigating LER and/or standing wave expression, wherein the shrink component is employed to heat a particular resist to the glass transition temperature of the resist to effectuate mitigation of LER and/or standing wave expression. Additionally, by heating the resist to its glass transition temperature, the systems and methods of the present invention effectively impede deviation from a desired target critical dimension.

Abstract translation: 本发明一般涉及光刻系统和方法，更具体地涉及有助于在集成电路中的图案线形成期间减少线边缘粗糙度（LER）和/或驻波表达的系统和方法。 公开了用于保持光致抗蚀剂线的目标临界尺寸（CD）的系统和方法，其包括有助于减轻LER和/或驻波表达的非光刻收缩组分，其中采用收缩组分将特定抗蚀剂加热到玻璃 抗蚀剂的转变温度来实现LER和/或驻波表达的缓解。 此外，通过将抗蚀剂加热至其玻璃化转变温度，本发明的系统和方法有效地阻止了偏离所需目标临界尺寸。

公开(公告)号：US07052921B1

公开(公告)日：2006-05-30

申请号：US10934192

申请日：2004-09-03

Applicant: Marina V. Plat ,  Bhanwar Singh ,  Calvin T. Gabriel ,  Christopher F. Lyons ,  Scott A. Bell ,  Ramkumar Subramanian ,  Srikanteswara Dakshina-Murthy

Inventor： Marina V. Plat ,  Bhanwar Singh ,  Calvin T. Gabriel ,  Christopher F. Lyons ,  Scott A. Bell ,  Ramkumar Subramanian ,  Srikanteswara Dakshina-Murthy

IPC: H01L21/66

CPC classification number: G03F7/70625 ,  G03F7/70608 ,  H01L22/12

Abstract: The present invention uses in situ scatterometry to determine if a defect (e.g., photoresist erosion, photoresist bending and pattern collapse) is present on a wafer. In one embodiment, in situ scatterometry is used to detect a pattern integrity defect associated with the layer of photoresist. In situ scatterometry produces diffraction data associated with the thickness of the photoresist patterned mask. This data is compared to a model of diffraction data associated with a suitable photoresist thickness. If the measured diffraction data is within an acceptable range, the next step of the photolithography process is carried out. However, if the measured thickness is outside of the suitable range, a defect is detected, and the wafer may be sent for re-working or re-patterned prior to main etch, thereby preventing unnecessary wafer scrap. Another aspect of the present invention allows for a feedback control mechanism to alter a physical parameter of the photolithographic process based upon the in situ scatterometry measurements.

Abstract translation: 本发明使用原位散射法来确定晶片上是否存在缺陷（例如，光致抗蚀剂侵蚀，光致抗蚀剂弯曲和图案崩溃）。 在一个实施例中，原位散射法用于检测与光致抗蚀剂层相关联的图案完整性缺陷。 原位散射法产生与光致抗蚀剂图案掩模的厚度相关的衍射数据。 将该数据与与合适的光致抗蚀剂厚度相关联的衍射数据的模型进行比较。 如果测量的衍射数据在可接受的范围内，则进行光刻工艺的下一步骤。 然而，如果测量的厚度在合适的范围之外，则检测到缺陷，并且可以在主蚀刻之前将晶片发送用于再加工或重新图案化，从而防止不必要的晶片废料。 本发明的另一方面允许反馈控制机制基于原位散射测量来改变光刻工艺的物理参数。