公开(公告)号：WO2007031395A1

公开(公告)日：2007-03-22

申请号：PCT/EP2006/065683

申请日：2006-08-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  CHINTHAKINDI, Anil, Kumar ,  COOLBAUGH, Douglas, Duane ,  DOWNES, Keith, Edward ,  ESHUN, Ebenezer ,  HE, Zhong-Xiang ,  RASSEL, Robert, Mark ,  STAMPER, Anthony, Kendall ,  VAED, Kunal

Inventor： CHINTHAKINDI, Anil, Kumar ,  COOLBAUGH, Douglas, Duane ,  DOWNES, Keith, Edward ,  ESHUN, Ebenezer ,  HE, Zhong-Xiang ,  RASSEL, Robert, Mark ,  STAMPER, Anthony, Kendall ,  VAED, Kunal

IPC: H01L21/02

CPC classification number: H01L28/40

Abstract: A Metal Insulator-Metal (MIM) capacitor is formed on a semiconductor substrate with a base comprising a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. An ancillary MIM capacitor plate is selected either a lower electrode formed on the STI region in the semiconductor substrate or a doped well formed in the top surface of the semiconductor substrate. A capacitor HiK dielectric layer is formed on or above the MIM capacitor lower plate. A second MIM capacitor plate is formed on the HiK dielectric layer above the MIM capacitor lower plate.

Abstract translation: 金属绝缘体 - 金属（MIM）电容器形成在半导体衬底上，其基底包括具有顶表面的半导体衬底，并且包括形成在从浅沟槽隔离（STI）区域中形成的区域和具有外表面的掺杂阱 与半导体衬底共面。 辅助MIM电容器板选择形成在半导体衬底中的STI区域上的下电极或形成在半导体衬底的顶表面中的掺杂阱。 在MIM电容器下板上形成电容器HiK电介质层。 在MIM电容器下板上方的HiK电介质层上形成第二MIM电容器板。

公开(公告)号：WO2005117085A3

公开(公告)日：2006-10-12

申请号：PCT/US2005018050

申请日：2005-05-23

Applicant: IBM ,  STAMPER ANTHONY K

Inventor： STAMPER ANTHONY K

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/31116 ,  H01L21/76807 ,  H01L28/87

Abstract: A method of forming a semiconductor device, and the device so formed. Depositing alternating layers of a first dielectric material (12a-f) and a second dielectric material (14a-f), wherein the first and second dielectric materials are selectively etchable at different rates. Forming a first feature (22, 24) within the alternating layers of dielectric material. Selectively etching the alternating layers of dielectric material to remove at least a portion (26) of the first dielectric material in each layer having the first dielectric material and leaving the second dielectric material as essentially unetched.

Abstract translation: 形成半导体器件的方法以及如此形成的器件。 沉积第一介电材料（12a-f）和第二介电材料（14a-f）的交替层，其中所述第一和第二介电材料可以以不同的速率被选择性地蚀刻。 在电介质材料的交替层内形成第一特征（22,24）。 选择性地蚀刻介电材料的交替层以去除具有第一电介质材料的每层中的第一介电材料的至少一部分（26），并使第二介电材料基本上未被蚀刻。

公开(公告)号：WO2006060212A1

公开(公告)日：2006-06-08

申请号：PCT/US2005/042088

申请日：2005-11-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ADKISSON, James, W. ,  GAMBINO, Jeffrey, P. ,  JAFFE, Mark, D. ,  LEIDY, Robert, K. ,  STAMPER, Anthony, K.

Inventor： ADKISSON, James, W. ,  GAMBINO, Jeffrey, P. ,  JAFFE, Mark, D. ,  LEIDY, Robert, K. ,  STAMPER, Anthony, K.

IPC: H01L31/062 ,  H01L21/00

CPC classification number: H01L27/14685 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14687

Abstract: A CMOS image sensor array (100) and method of fabrication wherein the sensor includes Copper (Cu) metallization levels (M1, M2) allowing for incorporation of a thinner interlevel dielectric stack (13 Oa-c) with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure (135a, 135b) formed at locations between each array pixel and, a barrier material layer (132a, 132b) is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening (51) is then refilled with dielectric material (150). Prior to depositing the refill dielectric, a layer of either reflective or absorptive material (140) is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode (18) or by eliminating light reflections.

Abstract translation: CMOS图像传感器阵列（100）及其制造方法，其中传感器包括铜（Cu）金属化水平（M1，M2），允许结合更薄的层间电介质堆叠（13a-c），具有改善的厚度均匀性，从而导致 显示增加的光敏度的像素阵列。 在传感器阵列中，每个Cu金属化层包括形成在每个阵列像素之间的位置处的Cu金属线结构（135a，135b），并且在每个Cu金属线结构上方形成阻挡材料层（132a，132b） 像素光路。 通过实现单掩模或自对准掩模方法，进行单次蚀刻以完全去除穿过光路的层间电介质层和阻挡层。 蚀刻的开口（51）然后用电介质材料（150）重新填充。 在沉积再充填电介质之前，沿蚀刻开口的侧壁形成反射或吸收材料层（140），以通过将光反射到下面的光电二极管（18）或通过消除光反射来提高像素的灵敏度。