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    CURRENT LIMITING CIRCUIT
    52.
    发明申请
    CURRENT LIMITING CIRCUIT 有权
    电流限制电路

    公开(公告)号：US20140327419A1

    公开(公告)日：2014-11-06

    申请号：US14267957

    申请日：2014-05-02

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.

    Inventor： Ni Zeng

    IPC: G05F1/573

    CPC classification number: G05F1/573

    Abstract: A current limiting circuit includes a current sensing module that is configured to sense an output current of a power transistor and to generate a corresponding sensing current which is proportional to the output current. A first current limiting module coupled to the current sensing module is configured to generate a first limiting current based on the sensing current when a variation of the output current of the power transistor exceeds a first current level. A second current limiting module coupled to the current sensing module is configured to generate a second limiting current based on the sensing current when a variation of the output current of the power transistor exceeds a second current level. A converting module coupled to the first and second current limiting modules and the power transistor controls a gate voltage of the power transistor based at least on the first and second limiting currents.

    Abstract translation: 电流限制电路包括电流感测模块，其被配置为感测功率晶体管的输出电流并产生与输出电流成比例的相应感测电流。 耦合到电流感测模块的第一限流模块被配置为当功率晶体管的输出电流的变化超过第一电流电平时，基于感测电流产生第一极限电流。 耦合到电流感测模块的第二限流模块被配置为当功率晶体管的输出电流的变化超过第二电流电平时，基于感测电流产生第二极限电流。 耦合到第一和第二限流模块的转换模块和功率晶体管至少基于第一和第二限制电流来控制功率晶体管的栅极电压。

    DRIVING CIRCUIT AND DISPLAY DEVICE
    53.
    发明申请
    DRIVING CIRCUIT AND DISPLAY DEVICE 审中-公开
    驱动电路和显示设备

    公开(公告)号：US20130169610A1

    公开(公告)日：2013-07-04

    申请号：US13648826

    申请日：2012-10-10

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.

    Inventor： Tao Tao Huang ,  Meng Wang

    IPC: G09G5/00 ,  H03K3/00

    CPC classification number: G09G3/36 ,  G09G3/3696

    Abstract: A driving circuit includes a controller, a converter and a feedback module. The controller receives an input supply at a supply node, and generates a control signal according to the input supply. The converter receive an input signal at an input node and a control signal at a control node, and is configured to convert the input signal to a driving signal in response to the control signal. The driving signal of the converter is feedback by the feedback module to the controller. The input supply is generated from the input signal or the feedback driving signal. The drive circuit may drive a display device.

    Abstract translation: 驱动电路包括控制器，转换器和反馈模块。 控制器在供电节点处接收输入电源，并根据输入电源产生控制信号。 转换器在输入节点处接收输入信号并在控制节点接收控制信号，并且被配置为响应于控制信号将输入信号转换成驱动信号。 转换器的驱动信号由反馈模块反馈给控制器。 输入电源由输入信号或反馈驱动信号产生。 驱动电路可以驱动显示装置。

    INVERTER AND METHOD FOR MEASURING PHASE CURRENTS IN AN ELECTRIC MACHINE
    54.
    发明申请
    INVERTER AND METHOD FOR MEASURING PHASE CURRENTS IN AN ELECTRIC MACHINE 有权

    公开(公告)号：US20210172983A1

    公开(公告)日：2021-06-10

    申请号：US16746444

    申请日：2020-01-17

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Shenzhen) R&D Co. Ltd

    Inventor： Dino COSTANZO ,  Cheng Pan CAI ,  Xi Yu XU

    IPC: G01R19/25 ,  G01R15/14 ,  H02P27/08 ,  H02M1/00 ,  H02M7/5387

    Abstract: A three-phase load is powered by a PWM (e.g., SVPWM) driven DC-AC inverter having a single shunt-topology. A shunt voltage and a branch voltage of the inverter (across a transistor to be calibrated) are measured during a second period of each SVPWM sector, and the drain-to-source resistance of the calibrated transistor is calculated. During the fourth period of each SVPWM sector, the branch voltage is measured again, and another branch voltage across another transistor is measured. Using the drain-to-source resistance of the calibrated transistor and the voltage across the calibrated transistor measured during the fourth period, the phase current through the calibrated transistor is calculated. Using the other branch voltage measured during the fourth period and the drain-to-source resistance of its corresponding transistor (known from a prior SVPWM sector), the phase current through that transistor is calculated. From the two calculated phase currents, the other phase current can be calculated.

    Audio amplifier with embedded buck controller for class-G application
    55.
    发明授权
    Audio amplifier with embedded buck controller for class-G application 有权

    公开(公告)号：US11018644B2

    公开(公告)日：2021-05-25

    申请号：US16695010

    申请日：2019-11-25

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.

    Inventor： XiangSheng Li ,  Ru Feng Du

    IPC: H03G3/30 ,  H03F3/187 ,  H04R3/00 ,  H04R29/00

    Abstract: An audio amplifier includes: a buck controller configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to receive a processed digital stream and provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, where the delay time is based on the settling time; and an audio amplitude detector configured to detect a first peak amplitude in the first digital audio stream, where the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage.

    Two-stage error amplifier with nested-compensation for LDO with sink and source ability
    56.
    发明授权
    Two-stage error amplifier with nested-compensation for LDO with sink and source ability 有权

    公开(公告)号：US10725488B2

    公开(公告)日：2020-07-28

    申请号：US15679274

    申请日：2017-08-17

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd

    Inventor： Ni Zeng

    IPC: G05F1/575

    Abstract: A low dropout amplifier may include an error amplifier having first and second inputs coupled to a reference signal and a feedback signal, respectively. The error amplifier may be configured to generate first and second error signals at first and second outputs, respectively, with the first and second error signals based upon a difference between the reference signal and the feedback signal. A sink stage may be coupled to the first output and configured to generate a sink current based upon the first error signal. A source stage may be coupled to the second output and configured to generate a source current based upon the second error signal. An output node may be coupled to receive the sink and source currents.

    CURRENT SENSING CIRCUIT AND METHOD
    57.
    发明申请
    CURRENT SENSING CIRCUIT AND METHOD 审中-公开

    公开(公告)号：US20190049511A1

    公开(公告)日：2019-02-14

    申请号：US16057089

    申请日：2018-08-07

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Shenzhen) R&D Co, Ltd.

    Inventor： Edoardo Botti ,  Davide Luigi Brambilla ,  Hong Wu Lin

    IPC: G01R31/26 ,  H03K17/687 ,  G01R19/00

    Abstract: A circuit includes a field effect transistor having a gate driven via a drive signal. The field effect transistor has a drain-source voltage drop indicative of the intensity of a current flowing in the current path through the field effect transistor. The circuit also includes a pair of sensing transistors that include a first sensing field effect transistor arranged with its drain and gate coupled with the drain and the gate of the field effect transistor, respectively, and a second sensing field effect transistor having a gate configured for receiving a replica of the drive signal. The second sensing field effect transistor is arranged with its current path in series with the current path of the first sensing field effect transistor. A sensing signal at a sensing node is indicative of the current intensity flowing in the current path of the field effect transistor.

    Methods and circuits to reduce pop noise in an audio device
    58.
    发明授权
    Methods and circuits to reduce pop noise in an audio device 有权

    公开(公告)号：US10193506B2

    公开(公告)日：2019-01-29

    申请号：US15377929

    申请日：2016-12-13

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd

    Inventor： Ru Feng Du ,  Qi Yu Liu

    IPC: H03F1/32 ,  H03G3/34 ,  H03F3/45 ,  H03F3/187 ,  H03F3/217 ,  H03F1/02 ,  H04R3/00 ,  H03F1/30 ,  H03F3/183 ,  H03F3/185 ,  H03F3/21

    Abstract: A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.

    Proximity detector device with interconnect layers and related methods
    59.
    发明授权
    Proximity detector device with interconnect layers and related methods 有权

    公开(公告)号：US10141471B2

    公开(公告)日：2018-11-27

    申请号：US15668138

    申请日：2017-08-03

    Applicant: STMICROELECTRONICS (SHENZHEN) R&D CO., LTD.

    Inventor： Jing-En Luan

    IPC: H01L31/173 ,  H01L31/0203 ,  H01L31/0232 ,  G01S7/481 ,  G01S17/02 ,  G01S17/08 ,  H01L23/00

    Abstract: A proximity detector device may include a first interconnect layer including a first dielectric layer, and first electrically conductive traces carried thereby, an IC layer above the first interconnect layer and having an image sensor IC, and a light source IC laterally spaced from the image sensor IC. The proximity detector device may include a second interconnect layer above the IC layer and having a second dielectric layer, and second electrically conductive traces carried thereby. The second interconnect layer may have first and second openings therein respectively aligned with the image sensor IC and the light source IC. Each of the image sensor IC and the light source IC may be coupled to the first and second electrically conductive traces. The proximity detector device may include a lens assembly above the second interconnect layer and having first and second lenses respectively aligned with the first and second openings.

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