公开(公告)号：WO2006128093A3

公开(公告)日：2007-02-22

申请号：PCT/US2006020658

申请日：2006-05-26

Applicant: SONY COMPUTER ENTERTAINMENT INC ,  CORSON GREGORY A

Inventor： CORSON GREGORY A

IPC: G09G5/08 ,  G06F3/00

CPC classification number: G06F3/0325 ,  G06F3/0304 ,  G06F3/0346

Abstract: An input device providing users with a pointing capability includes a sender portion (100) and a receiver portion (200). The sender portion ( 100) is adapted to be manipulated by a user (the user manipulating button 125) to specify a target point within a target area. The sender portion projects a light beam (light output from light source 115) including a pattern onto the target area. A receiver portion (200) includes one or more sensor units (205, 210, 215) located in or near the target area. At least some of the sensor units (205, 210, 215) receive a portion of the light beam (light output from light source 115) regardless of the location of the target point within the target area. A processing unit (220) in the receiver portion (200) analyzes the portions of the light beam received by one or more sensor units (205, 210, 215) to determine an attribute of the target point. The attribute can be the location or relative motion of the target point. The receiver portion (200) may be integrated with a display device.

Abstract translation: 向用户提供指向能力的输入设备包括发送器部分（100）和接收器部分（200）。 发送器部分（100）适于由用户（用户操纵按钮125）操纵以指定目标区域内的目标点。 发送器部分将包括图案的光束（从光源115输出的光）投射到目标区域上。 接收器部分（200）包括位于目标区域中或附近的一个或多个传感器单元（205,210,215）。 至少一些传感器单元（205,210,215）接收光束的一部分（从光源115输出的光），而不管目标区域内的目标点的位置如何。 接收器部分（200）中的处理单元（220）分析由一个或多个传感器单元（205,210,215）接收的光束的部分，以确定目标点的属性。 属性可以是目标点的位置或相对运动。 接收器部分（200）可以与显示装置集成。

公开(公告)号：WO2006083046A3

公开(公告)日：2007-02-08

申请号：PCT/JP2006302428

申请日：2006-02-07

Applicant: SONY COMPUTER ENTERTAINMENT INC ,  YASUE MASAHIRO

Inventor： YASUE MASAHIRO

IPC: G06F9/48

CPC classification number: G06F9/4843 ,  G06F8/45

Abstract: Methods and apparatus provide for executing one or more software programs within a plurality of processors of a multi-processing system in accordance with a data parallel processing model, the software programs being comprised of a number of processing tasks, each task executing instructions on one or more input data units to produce an output data unit, and each data unit containing one or more data objects; responding to one or more application programming interface codes to change from a current processing task to a subsequent processing task within a given one or more of the processors; and using the output data unit produced by the current processor task as an input data unit by the subsequent processing task to produce a further output data unit within the same processor.

Abstract translation: 方法和装置提供了根据数据并行处理模型在多处理系统的多个处理器内执行一个或多个软件程序，该软件程序由许多处理任务组成，每个任务在一个或多个处理系统上执行指令 更多的输入数据单元以产生输出数据单元，每个数据单元包含一个或多个数据对象; 响应于一个或多个应用程序编程接口代码从当前处理任务改变为给定的一个或多个处理器内的后续处理任务; 并且通过后续处理任务将由当前处理器任务产生的输出数据单元用作输入数据单元，以在同一处理器内产生另外的输出数据单元。

公开(公告)号：WO2006121201A1

公开(公告)日：2006-11-16

申请号：PCT/JP2006/309880

申请日：2006-05-11

Applicant: SONY COMPUTER ENTERTAINMENT INC.

Inventor： OHTSUKA, Katsushi

IPC: G06F9/46

CPC classification number: G06F9/4812

Abstract: An even-driven interrupt processing is efficiently carried out in a multiprocessor system. A main control unit 112 executes a main process as a processing for controlling an apparatus in a unified manner. A sub-control unit 116 executes a task assigned by the main control unit 112 during the execution of the main process, as a sub-process. An event detector 162 detects an event occurrence upon which an interrupt task is to be preferentially executed during the execution of the main process. An interrupt notification unit 164 notifies the sub-control unit 116 of interrupt information indicative of an interrupt task in response to the detected event. The sub-control unit 116 notified of the interrupt information executes the interrupt task specified by the interrupt information, as a sub-process.

Abstract translation: 在多处理器系统中有效地执行均匀驱动的中断处理。 主控制单元112执行作为用于统一控制装置的处理的主处理。 子控制单元116在执行主处理期间执行由主控制单元112分配的任务作为子处理。 事件检测器162检测在执行主处理期间优先执行中断任务的事件发生。 中断通知单元164响应于检测到的事件向子控制单元116通知指示中断任务的中断信息。 通知中断信息的子控制单元116执行由中断信息指定的中断任务作为子处理。

公开(公告)号：WO2006120408A3

公开(公告)日：2006-11-16

申请号：PCT/GB2006/001660

申请日：2006-05-05

Applicant: SONY COMPUTER ENTERTAINMENT INC. ,  EZRA, Rabin

Inventor： EZRA, Rabin

IPC: G06F9/38 ,  G06F12/08

Abstract: A data processor comprises a main memory; an instruction cache and a data cache; instruction fetch logic operable to search the instruction cache for a required instruction; and if the required instruction is not present in the instruction cache, to search the data cache; and if the required instruction is not present in the data cache, to fetch the required instruction from the main memory to the instruction cache; data write logic operable to write a data value into the data cache at a data address and, if that address is also represented in the instruction cache, to write that data value into the instruction cache; and cache control logic operable to transfer data from the data cache to the main memory.

公开(公告)号：WO2006120408A2

公开(公告)日：2006-11-16

申请号：PCT/GB2006001660

申请日：2006-05-05

Applicant: SONY COMPUTER ENTERTAINMENT INC ,  EZRA RABIN

Inventor： EZRA RABIN

IPC: G06F9/38 ,  G06F12/08

CPC classification number: G06F12/0848 ,  G06F9/3802 ,  G06F9/3812

Abstract: A data processor comprises a main memory; an instruction cache and a data cache; instruction fetch logic operable to search the instruction cache for a required instruction; and if the required instruction is not present in the instruction cache, to search the data cache; and if the required instruction is not present in the data cache, to fetch the required instruction from the main memory to the instruction cache; data write logic operable to write a data value into the data cache at a data address and, if that address is also represented in the instruction cache, to write that data value into the instruction cache; and cache control logic operable to transfer data from the data cache to the main memory.

Abstract translation: 数据处理器包括主存储器; 指令高速缓存和数据高速缓存; 指令提取逻辑，用于搜索所述指令高速缓存以获得所需指令; 并且如果指令高速缓存中不存在所需指令，则搜索数据高速缓存; 并且如果在数据高速缓存中不存在所需指令，则从主存储器获取所需指令到指令高速缓存; 数据写入逻辑可操作以将数据值写入数据高速缓存中的数据地址，并且如果该地址也在指令高速缓存中表示，则将该数据值写入指令高速缓存; 以及高速缓存控制逻辑，用于将数据从数据高速缓存传送到主存储器。

公开(公告)号：WO2006085641A1

公开(公告)日：2006-08-17

申请号：PCT/JP2006/302425

申请日：2006-02-07

Applicant: SONY COMPUTER ENTERTAINMENT INC. ,  SUZUOKI, Masakazu

Inventor： SUZUOKI, Masakazu

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: Methods and apparatus provide for assigning an identifier to a DMA command, the identifier for association with an entry of a DMA table containing status information regarding the DMA command; receiving an indication that a DMA data transfer defined by the DMA command has been completed; and updating the status information of the entry of the DMA table associated with the DMA data transfer to indicate that the DMA data transfer has been completed.

Abstract translation: 方法和装置提供将标识符分配给DMA命令，该标识符与包含关于DMA命令的状态信息的DMA表的条目相关联; 接收由DMA命令定义的DMA数据传输已经完成的指示; 以及更新与DMA数据传输相关联的DMA表的条目的状态信息，以指示DMA数据传送已经完成。

公开(公告)号：WO2006085639A2

公开(公告)日：2006-08-17

申请号：PCT/JP2006/302422

申请日：2006-02-07

Applicant: SONY COMPUTER ENTERTAINMENT INC. ,  SUZUOKI, Masakazu

Inventor： SUZUOKI, Masakazu

CPC classification number: G06F9/5044 ,  G06F8/52 ,  G06F2209/549

Abstract: Methods and apparatus provide for translating a software program page by page from a first instruction set architecture (ISA) into a second ISA using one or more of a set of processors of a multi-processor system; and executing the translated software program using a dedicated other processor of the multi-processor system.

Abstract translation: 方法和装置提供使用多处理器系统的一组处理器中的一个或多个从第一指令集架构（ISA）逐页翻译软件程序到第二ISA的方法和装置; 以及使用所述多处理器系统的专用其他处理器来执行所述翻译的软件程序。

公开(公告)号：WO2006085636A1

公开(公告)日：2006-08-17

申请号：PCT/JP2006/302419

申请日：2006-02-07

Applicant: SONY COMPUTER ENTERTAINMENT INC.

Inventor： YAMAZAKI, Takeshi

IPC: G06F9/38

CPC classification number: G06F9/3802 ,  G06F9/30087 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3885

Abstract: Methods and apparatus provide for transferring blocks of data between a shared memory and one or more of a plurality of parallel processors, each processor including a local memory; executing one or more programs within the local memory of one or more of the processors, wherein the one or more programs are coded such that they do not rely on data caching within the processor; and buffering not more than about three instructions from any local memory in any instruction buffer of any processor, wherein the instruction buffer of each processor is adapted to process instructions with substantially maximal efficiency when the one or more programs are coded such that they do not rely on data caching within the processor.

Abstract translation: 方法和装置提供用于在共享存储器与多个并行处理器中的一个或多个并行处理器之间传送数据块，每个处理器包括本地存储器; 在一个或多个处理器的本地存储器内执行一个或多个程序，其中所述一个或多个程序被编码，使得它们不依赖于处理器内的数据高速缓存; 并且在任何处理器的任何指令缓冲器中从任何本地存储器缓冲不超过约三条指令，其中每个处理器的指令缓冲器适于在一个或多个程序被编码时以基本上最大的效率来处理指令，使得它们不依赖 在处理器内的数据缓存。

公开(公告)号：WO2006082994A2

公开(公告)日：2006-08-10

申请号：PCT/JP2006/302107

申请日：2006-02-01

Applicant: SONY COMPUTER ENTERTAINMENT INC.

Inventor： HATAKEYAMA, Akiyuki

CPC classification number: G06F12/1408 ,  G06F21/575

Abstract: Methods and apparatus provide for verifying operating system software integrity prior to being executed by a processor, the processor including an associated local memory and capable of operative connection to a main memory such that data may be read from the main memory for use in the local memory; storing a status flag indicating whether the operating system software integrity is or is not satisfactory; and ensuring that the status flag indicates that the operating system software integrity is satisfactory before permitting the processor to continue in a course of action.

Abstract translation: 方法和装置提供在由处理器执行之前验证操作系统软件完整性，处理器包括相关联的本地存储器并且能够与主存储器的操作连接，使得可以从主存储器读取数据以用于本地存储器 ; 存储指示操作系统软件完整性是否满意的状态标志; 并且在允许处理器在操作过程中继续的情况下，确保状态标志指示操作系统软件完整性令人满意。

公开(公告)号：WO2006082985A2

公开(公告)日：2006-08-10

申请号：PCT/JP2006/302095

申请日：2006-02-01

Applicant: SONY COMPUTER ENTERTAINMENT INC.

Inventor： HATAKEYAMA, Akiyuki

CPC classification number: G06F21/51 ,  G06F21/57 ,  G06F21/575 ,  G06F2221/2105 ,  G06F2221/2107 ,  H04L9/3236 ,  H04L2209/125

Abstract: Methods and apparatus provide for: reading encrypted boot code from a storage medium into a local memory associated with a first of a plurality of processors; decrypting the encrypted boot code using a trusted decryption function of the first processor such that the boot code is verified as being authentic; booting the first processor using the boot code from the local memory; and authenticating boot code for one or more of the other processors in the first processor prior to the one or more other processors booting up.

Abstract translation: 方法和装置提供：从存储介质读取加密的引导代码到与多个处理器中的第一个处理器相关联的本地存储器中; 使用所述第一处理器的可信解密功能来解密所述经加密的引导代码，使得所述引导代码被验证为可信的; 使用来自本地存储器的引导代码引导第一处理器; 以及在所述一个或多个其他处理器启动之前，对第一处理器中的一个或多个其他处理器的启动代码进行认证。