公开(公告)号：KR1020100062893A

公开(公告)日：2010-06-10

申请号：KR1020090076780

申请日：2009-08-19

Applicant: 삼성전자주식회사 ,  서울대학교산학협력단

Inventor： 오도환 ,  정덕균 ,  추교진

IPC: H03M1/50 ,  H03L7/081

Abstract: PURPOSE: A time to digital converter and a digital phase-locked loop are provided to improve a phase-alignment accuracy by detecting not only a phase error but also a frequency error. CONSTITUTION: A converter(120) receives a first signal and a second signal. The converter gradually delays the second signal using delay elements. The converter outputs the phase error of the second signal about the first signal. A phase frequency detector(110) receives a third signal from one node among the first signal and the node of a plurality of delay elements. The phase-frequency detector outputs a phase difference about the first signal and the third signal. A frequency detector(130) outputs the frequency error of the second signal about the first signal to a digital code using the second signal and the output signal of the phase-frequency detector.

Abstract translation: 目的：提供数字转换器和数字锁相环的时间，通过不仅检测相位误差而且通过检测频率误差来提高相位对准精度。 构成：A转换器（120）接收第一信号和第二信号。 转换器使用延迟元件逐渐延迟第二信号。 转换器输出关于第一信号的第二信号的相位误差。 相位频率检测器（110）从多个延迟元件的第一信号和节点中的一个节点接收第三信号。 相位频率检测器输出关于第一信号和第三信号的相位差。 频率检测器（130）使用第二信号和相位 - 频率检测器的输出信号将关于第一信号的第二信号的频率误差输出到数字码。