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公开(公告)号：KR1019960007676B1
公开(公告)日：1996-06-08
申请号：KR1019930004205
申请日：1993-03-18
IPC: H04L12/28
Abstract: an AND operating means 24 for performing an AND operation with a data transition demixible signal and a clock; parallel input line means A0-A7 for parallelly transferring the ATM cell information of the 1-octet; a memory means 21 for inputting a clear signal to set all intial values to "0", inputting the output signal from the AND operating means 24 to a clock port and inputting an input signal from the parallel input lines A0-A7; a control means 21 for inputting the output of the memory means 22 and the data transition demixible signal(DSCENA); and an operating means 22 for inputting the control signal from the controlling means 21 and the output of the parallel input line means A0-A7, and outputting mixed signals B7-B0.
Abstract translation: AND操作装置24，用于执行与数据转换可分辨信号和时钟的“与”运算; 并行输入线装置A0-A7，用于并行传送1个字节的ATM信元信息; 存储装置21，用于输入清除信号以将所有初始值设置为“0”，将来自AND操作装置24的输出信号输入到时钟端口并输入来自并行输入线A0-A7的输入信号; 用于输入存储装置22的输出和数据转换可分辨信号（DSCENA）的控制装置21; 以及用于输入来自控制装置21的控制信号和并行输入线装置A0-A7的输出的操作装置22，并输出混合信号B7-B0。
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53.发明授权
公开(公告)号：KR1019950013847B1
公开(公告)日：1995-11-16
申请号：KR1019930004207
申请日：1993-03-18
IPC: H04L12/28
CPC classification number: H04L9/12 , H04L9/0656
Abstract: The circuit for processing the transmitted data with parallel 8 bit by using ordinary semiconductor element includes a line matching circuit(11) sampling the clock and receiving data, a processor(12) determining the cell boundary after calculating the syndrome with HEC code, a DSS demultiplexer(13) demultiplexing the input data, a cell processor(14) transferring the ATM cell layer, and an processor maintaining the OAM cell separated by the processor(14).
Abstract translation: 通过使用普通半导体元件对并行8位发送的数据进行处理的电路包括对时钟进行采样和接收数据的线路匹配电路（11），用HEC码计算综合征之后确定小区边界的处理器（12），DSS 多路分解器（13）对输入数据进行解复用，传送ATM信元层的信元处理器（14）和维护由处理器（14）分离的OAM信元的处理器。
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Patent Agency Ranking
公开(公告)号：KR1019950005989B1
公开(公告)日：1995-06-07
申请号：KR1019910024045
申请日：1991-12-23
IPC: H04M3/22
Abstract: The method tests the various transmission characteristic of the relay unit utilizing the internal test unit. The method comprises the steps of: hooking up the communication line through the relay unit; composing the test line as delivering the test request; measuring the transmission quality with the transmission request; and ending up the system test.
Abstract translation: 该方法利用内部测试单元测试中继单元的各种传输特性。 该方法包括以下步骤：通过中继单元挂接通信线路; 组成测试线提供测试请求; 用传输请求测量传输质量; 并结束系统测试。
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公开(公告)号：KR1019930015553A
公开(公告)日：1993-07-24
申请号：KR1019910026048
申请日：1991-12-30
IPC: H04M3/22
Abstract: 본 발명은 중계선 시험장치를 구비하여 전전자 교환기의 디지틀 중계선의 BER 시험 수행 방법에 있어서, 운용자가 상기 전전자 교환기의 운용단말기를 통해 중계선 시험 명령어를 입력하면 상기 전전자 교환기에서는 시험준비를 수행한 후 상기 중계선 시험장치로 시험회선 연결 요구를 하는 제1단계, 대국으로 루프백 호 경로를 구성하도록 요구하여 BER 시험을 수행하는 제2단계, 착신측 교환기는 루프백 호 경로 구성 요구에 따라 해당 중계선으로 루프백 호 경로를 구성하는 제3단계 및 교환기는 시험결과를 받으면 시험회선 복구를 요구하고 대국으로 중계선 복구를 통보하고 통화로를 절단한뒤 중계선의 상태를 서비스가능한 상태로 변경하고 시험결과를 출력하여 운용자에게 알리는 제4단계를 구비하고 있는 것을 특징으로 한다.
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公开(公告)号：KR1020090059430A
公开(公告)日：2009-06-11
申请号：KR1020070126290
申请日：2007-12-06
CPC classification number: H04L1/0013 , H03M13/2778 , H03M13/2792
Abstract: An apparatus and a method for processing a signal are provided to consecutively encode a plurality of code blocks by collecting a rate matching result bit of an information bit and a parity bit into a bit stream. An encoder(150) encodes an input signal, and outputs an information bit, a first parity bit, and a second parity bit. A rate matching device(160) collects a rate matching result bit of the information bit, the first parity bit, and the second parity bit into a bit stream while rate-matching the information bit, the first parity bit, and the second parity bit. A block interleaver(170) block-interleaves the bit stream. A collecting period and a block interleaving period are overlapped.
Abstract translation: 提供了一种用于处理信号的装置和方法，用于通过将信息比特和奇偶校验比特的速率匹配结果比特收集到比特流中来对多个码块进行连续编码。 编码器（150）对输入信号进行编码，并输出信息比特，第一奇偶校验位和第二奇偶校验位。 速率匹配装置（160）将信息比特，第一奇偶校验位和第二奇偶校验比特的速率匹配结果比特收集到比特流中，同时对信息比特，第一奇偶校验位和第二奇偶校验位进行速率匹配 。 块交织器（170）块比特流进行交织。 收集周期和块交织周期重叠。
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公开(公告)号：KR100791228B1
公开(公告)日：2008-01-03
申请号：KR1020060112377
申请日：2006-11-14
Applicant: 한국전자통신연구원
IPC: H03M13/37
CPC classification number: H03M13/2975 , H03M13/2792 , H03M13/3753 , H04L1/0051
Abstract: An apparatus and a method for stopping iterative decoding using BIP(Bit Interleave Parity), and a turbo decoder using the same are provided to reduce the amount of hardware by preparing a memory device according to the length of BIP and comparing BIP values in parallel. An apparatus(31) for stopping iterative decoding using BIP includes a BIP calculating unit(311), a storage unit(312), a BIP comparing unit(313), and an iterative decoding stopping unit(314). The BIP calculating unit calculates the BIP for transmission data estimated through a decoding process in a turbo decoder(30). The storage unit stores the BIP(present BIP) for the transmission data estimated in the present decoding process, and the BIP(previous BIP) for the transmission data estimated in the previous decoding process. The BIP comparing unit compares the present BIP with the previous BIP to determine whether the BIPs are identical to each other. The iterative decoding stopping unit stops the iterative decoding process in the turbo decoder in case that the BIPs are identical to each other.
Abstract translation: 提供了使用BIP（比特交织奇偶校验）停止迭代解码的装置和方法，以及使用该解码器的Turbo解码器，通过根据BIP的长度准备存储器件并并行地比较BIP值来减少硬件的数量。 用于使用BIP停止迭代解码的装置（31）包括BIP计算单元（311），存储单元（312），BIP比较单元（313）和迭代解码停止单元（314）。 BIP计算单元计算在turbo解码器（30）中通过解码处理估计的传输数据的BIP。 存储单元存储用于在当前解码处理中估计的发送数据的BIP（当前BIP）和用于在先前解码处理中估计的发送数据的BIP（先前BIP）。 BIP比较单元将当前BIP与先前的BIP进行比较，以确定BIP是否彼此相同。 在BIP彼此相同的情况下，迭代解码停止单元停止turbo解码器中的迭代解码处理。
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