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51.发明授权公开(公告)号：US09653029B2
公开(公告)日：2017-05-16
申请号：US14558663
申请日：2014-12-02
Applicant: Apple Inc.
Inventor： Chaohao Wang , Szu-Hsien Lee , Paolo Sacchetto , Shih Chang Chang , Chun-Yao Huang , Paul S. Drzaic
CPC classification number: G09G3/3611 , G09G3/32 , G09G2310/04 , G09G2320/0247 , G09G2320/103 , G09G2340/0435
Abstract: This application relates to methods and apparatus for refreshing a display device at various frequencies. Specifically, multiple areas of the display device can be refreshed concurrently at different frequencies. In this way, when static content is being displayed in certain areas of the display device, those certain areas can be refreshed at a lower rate than areas displaying dynamic content such as video or animation. By refreshing at lower rates, the energy consumed by the display device and subsystems associated with the display device can be reduced. Additionally, processes for reducing flicker when refreshing the display device at different refresh rates are disclosed herein.
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公开(公告)号：US20170004790A1
公开(公告)日：2017-01-05
申请号：US14862071
申请日：2015-09-22
Applicant: Apple Inc.
Inventor： Rungrot Kitsomboonloha , Chun-Yao Huang , Kyung Wook Kim , Shih Chang Chang , Szu-Hsien Lee
CPC classification number: G09G3/3674 , G09G3/20 , G09G3/3225 , G09G3/3648 , G09G2300/0408 , G09G2310/0267 , G09G2310/0286 , G09G2310/0291
Abstract: A display is provided that includes an array of display pixels and gate driver circuitry for providing data and gate line signals to the display pixels. Gate driver circuitry may include gate driver circuits that generate the gate line signals. A gate driver circuit may include at least a buffer transistor, a bootstrapping capacitor coupled to the buffer transistor, a pulldown transistor coupled in series with the buffer transistor, and an isolation transistor coupled to the gate of the pulldown transistor. The buffer transistor may directly receive a first clock signal, whereas the isolation transistor may directly receive a second clock signal that is complementary to the first clock signal. The pulldown transistor is substantially larger than the buffer transistor. The buffer transistor is substantially larger than the isolation transistor. Configured as such, clock loading is minimized while the pulldown transistor is sized to provide the desired fall time performance.
Abstract translation: 提供了一种显示器，其包括用于向显示像素提供数据和栅极线信号的显示像素阵列和栅极驱动器电路。 栅极驱动器电路可以包括产生栅极线信号的栅极驱动器电路。 栅极驱动器电路可以包括至少缓冲晶体管，耦合到缓冲晶体管的自举电容器，与缓冲晶体管串联耦合的下拉晶体管，以及耦合到下拉晶体管的栅极的隔离晶体管。 缓冲晶体管可以直接接收第一时钟信号，而隔离晶体管可以直接接收与第一时钟信号互补的第二时钟信号。 下拉晶体管实质上大于缓冲晶体管。 缓冲晶体管基本上大于隔离晶体管。 如此配置，时钟负载最小化，而下拉晶体管的尺寸设置为提供所需的下降时间性能。
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公开(公告)号：US09466018B2
公开(公告)日：2016-10-11
申请号：US14699417
申请日：2015-04-29
Applicant: Apple Inc.
Inventor： Kwang Soon Park , Ming-Chin Hung , Chun-Yao Huang , Shih Chang Chang , Ming-Yuh Hsu
IPC: H04Q5/22 , G06K19/077 , G02F1/1335 , G02F1/1368 , G02F1/133 , G06K7/10 , G02F1/1333
CPC classification number: G06K19/0772 , G02F1/13306 , G02F1/133512 , G02F1/133528 , G02F1/1368 , G02F2001/133388 , G06K7/10198
Abstract: A display may have an active area surrounded by an inactive border area. The display may be a liquid crystal display having a liquid crystal layer sandwiched between a color filter layer and a thin-film transistor layer. An upper polarizer may have a polarized central region that overlaps the active area of the display. The upper polarizer may also have an unpolarized portion in the inactive border area overlapping the border structures. The border structures may include colored material such as a white layer on the inner surface of the thin-film transistor layer. Binary information may be embedded into an array of programmable resonant circuits. The binary information may be a display identifier or other information associated with a display. The programmable resonant circuits may be tank circuits with adjustable capacitors, fuses, or other programmable components.
Abstract translation: 显示器可以具有被非活动边界区域包围的活动区域。 显示器可以是具有夹在滤色器层和薄膜晶体管层之间的液晶层的液晶显示器。 上偏振器可以具有与显示器的有效区域重叠的偏振中心区域。 上偏振器还可以在非边界区域中具有与边界结构重叠的非偏振部分。 边界结构可以在薄膜晶体管层的内表面上包括诸如白色层的着色材料。 二进制信息可嵌入到可编程谐振电路阵列中。 二进制信息可以是与显示器相关联的显示标识符或其他信息。 可编程谐振电路可以是具有可调电容器，保险丝或其他可编程元件的储能电路。
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公开(公告)号：US20160293081A1
公开(公告)日：2016-10-06
申请号：US14677531
申请日：2015-04-02
Applicant: Apple Inc.
Inventor： Rungrot Kitsomboonloha , Chun-Yao Huang , Shih Chang Chang , Szu-Hsien Lee
CPC classification number: G06F3/0416 , G09G3/3677 , G09G2310/0202 , G09G2310/0218 , G09G2310/0267 , G09G2320/043
Abstract: A display may have an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The gate driver circuitry may include blocks of gate driver circuits each having an output coupled to a respective one of the gate lines. The gate driver circuits of each block are coupled in a chain to form a shift register. Each block has a local block-level gate start pulse generator. The display driver circuitry has a display driver circuit that supplies a gate start pulse clock to each of the local block-level gate start pulse generators. The local block-level gate start pulse generators create gate start pulses that are applied to the first gate driver circuit in each shift register. The display driver circuit may delay the gate start pulse clock when it is desired to implement an intraframe pause.
Abstract translation: 显示器可以具有由显示驱动器电路控制的像素阵列。 栅极驱动器电路将栅极线信号提供给像素的行。 栅极驱动器电路可以包括栅极驱动器电路块，每个栅极驱动器电路具有耦合到相应的一条栅极线的输出。 每个块的栅极驱动器电路被耦合在链中以形成移位寄存器。 每个块具有本地块级门控起始脉冲发生器。 显示驱动器电路具有显示驱动器电路，其向每个本地块级门控起始脉冲发生器提供栅极起始脉冲时钟。 局部块电平门起始脉冲发生器产生施加到每个移位寄存器中的第一栅极驱动器电路的栅极起始脉冲。 当期望实现帧内暂停时，显示驱动器电路可以延迟门启动脉冲时钟。
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公开(公告)号：US09367188B2
公开(公告)日：2016-06-14
申请号：US14286718
申请日：2014-05-23
Applicant: Apple Inc.
Inventor： Szu-Hsien Lee , Byung Duk Yang , Chun-Yao Huang , Kyung Wook Kim , Shih Chang Chang
IPC: G06F3/044
CPC classification number: G06F3/044 , G06F3/0416 , Y10T29/49107
Abstract: A touch screen. In some examples, the touch screen can comprise a first element coupled to a first sense connection, and a second element coupled to a second sense connection. In some examples, the first and second sense connections can be configured such that a load presented by the first sense connection and the first element is substantially equal to a load presented by the second sense connection and the second element. In some examples, the first and second sense connections can comprise detour routing configured such that a resistance of the first sense connection is substantially equal to a resistance of the second sense connection. In some examples, the first and second sense connections can be coupled to dummy routing configured such that a first capacitance presented by the first sense connection is substantially equal to a second capacitance presented by the second sense connection.
Abstract translation: 触摸屏。 在一些示例中，触摸屏可以包括耦合到第一感测连接的第一元件和耦合到第二感测连接的第二元件。 在一些示例中，第一和第二感测连接可以被配置为使得由第一感测连接和第一元件呈现的负载基本上等于由第二感测连接和第二元件呈现的负载。 在一些示例中，第一和第二感测连接可以包括被配置为使得第一感测连接的电阻基本上等于第二感测连接的电阻的迂回路由。 在一些示例中，第一感测连接和第二感测连接可以耦合到伪路由，其被配置为使得由第一感测连接呈现的第一电容基本上等于由第二感测连接呈现的第二电容。
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Patent Agency Ranking
56.发明授权公开(公告)号：US09269319B2
公开(公告)日：2016-02-23
申请号：US14502856
申请日：2014-09-30
Applicant: APPLE INC.
Inventor： Louis Luh , Chun-Yao Huang
CPC classification number: G09G3/3677 , G09G3/3266 , G09G2310/0286 , G09G2310/06 , G11C19/184 , G11C19/28
Abstract: One gate driver includes an output node configured to be coupled to a gate line and to provide power to the gate line for driving thin-film transistor (TFT) gates of a display. An input node of the gate driver is configured to receive an input signal. The gate driver includes a first field-effect transistor (FET) having a gate, a drain, and a source. The drain may be coupled to the input node and the source may be coupled to the output node. The gate driver also includes a second FET having a gate, a drain, and a source. The drain may be coupled to the input node. The gate driver includes a capacitor having a first end coupled to the gates of the FETs and a second end coupled to the source of the second FET. Using the gate driver power consumption of the display may be reduced.
Abstract translation: 一个栅极驱动器包括被配置为耦合到栅极线并且向栅极线提供功率以用于驱动显示器的薄膜晶体管（TFT）栅极的输出节点。 栅极驱动器的输入节点被配置为接收输入信号。 栅极驱动器包括具有栅极，漏极和源极的第一场效应晶体管（FET）。 漏极可以耦合到输入节点，并且源可以耦合到输出节点。 栅极驱动器还包括具有栅极，漏极和源极的第二FET。 漏极可以耦合到输入节点。 栅极驱动器包括具有耦合到FET的栅极的第一端和耦合到第二FET的源极的第二端的电容器。 使用门驱动器可以降低显示器的功耗。
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公开(公告)号：US20150055047A1
公开(公告)日：2015-02-26
申请号：US14228070
申请日：2014-03-27
Applicant: Apple Inc.
Inventor： Shih Chang Chang , Ming-Chin Hung , Cheng-Ho Yu , Ting-Kuo Chang , Abbas Jamshidi Roudbari , Shang-Chih Lin , Kyung-Wook Kim , Chun-Yao Huang , Szu-Hsien Lee , Yu-Cheng Chen , Hiroshi Osawa
IPC: G02F1/1368
CPC classification number: H01L27/3262 , G02F1/13454 , G02F1/13624 , G02F1/1368 , G02F2001/13685 , G02F2202/104 , G09G3/3225 , G09G3/3611 , G09G3/3677 , G09G2320/043 , H01L27/1222 , H01L27/1225 , H01L27/1251 , H01L27/1255
Abstract: An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure.
Abstract translation: 电子设备可以包括在基板上具有显示像素阵列的显示器。 显示像素可以是液晶显示器中的有机发光二极管显示像素或显示像素。 在有机发光二极管显示器中，可以形成包括半导体氧化物薄膜晶体管，硅薄膜晶体管和电容器结构的混合薄膜晶体管结构。 电容器结构可以与半导体氧化物薄膜晶体管重叠。 有机发光二极管显示像素可以具有氧化物和硅晶体管的组合。 在液晶显示器中，显示驱动器电路可以包括硅薄膜晶体管电路，显示像素可以基于氧化物薄膜晶体管。 可以在形成硅晶体管栅极和氧化物晶体管栅极中使用单层或两层不同的栅极金属层。 硅晶体管可以具有与浮动栅极结构重叠的栅极。
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公开(公告)号：US08748320B2
公开(公告)日：2014-06-10
申请号：US13629547
申请日：2012-09-27
Applicant: Apple Inc.
Inventor： Ming-Chin Hung , Young Bae Park , Chun-Yao Huang , Shih Chang Chang , John Z. Zhong
IPC: H01L21/311
CPC classification number: H01L29/7869 , H01L27/124 , H01L27/1288 , H01L29/66969 , H01L29/78606
Abstract: A method of connecting to a first metal layer in a semiconductor flow process. Disclosed embodiments connect to the first metal layer by etching a first portion of a viahole through an etch stop layer and a gate insulation layer to reach a first metal layer, depositing a second metal layer such that the second metal layer contacts the first metal layer within the viahole, and etching a second portion of the viahole through a first passivation layer and an organic layer to reach the second metal layer.
Abstract translation: 一种在半导体流程中连接到第一金属层的方法。 公开的实施例通过蚀刻通孔的第一部分通过蚀刻停止层和栅极绝缘层连接到第一金属层，以到达第一金属层，沉积第二金属层，使得第二金属层与第一金属层接触， 所述通孔，并且通过第一钝化层和有机层蚀刻所述通孔的第二部分以到达所述第二金属层。
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公开(公告)号：US20250081730A1
公开(公告)日：2025-03-06
申请号：US18755498
申请日：2024-06-26
Applicant: Apple Inc.
Inventor： Andrew Lin , Alper Ozgurluk , Chao Liang Chien , Cheuk Chi Lo , Chia-Yu Chen , Chien-Chung Wang , Chih Pang Chang , Chih-Hung Yu , Chih-Wei Chang , Chin Wei Hsu , ChinWei Hu , Chun-Kai Tzeng , Chun-Ming Tang , Chun-Yao Huang , Hung-Che Ting , Jung Yen Huang , Lungpao Hsin , Shih Chang Chang , Tien-Pei Chou , Wen Sheng Lo , Yu-Wen Liu , Yung Da Lai
IPC: H10K59/121 , H10K59/131
Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.
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公开(公告)号：US12175943B2
公开(公告)日：2024-12-24
申请号：US17949949
申请日：2022-09-21
Applicant: Apple Inc.
Inventor： Bilin Wang , Tien-Chien Kuo , Kanghoon Jeon , Chun-Yao Huang
IPC: G09G3/30 , G09G3/3291 , G09G3/36 , G09G5/397
Abstract: A display system may include a memory external to a pixel that stores a first digital data value, a memory internal to the pixel that stores a second digital data signal, where a combination of the first digital data signal and the second digital data signal may indicate a target gray level assigned to the pixel for a particular image frame. The pixel may be driven for a first duration of time according to the first digital data signal and for a second duration of time according to the second digital data signal.
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