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    Security Enclave Processor for a System on a Chip
    51.
    发明申请
    Security Enclave Processor for a System on a Chip 有权
    用于芯片系统的安全处理器

    公开(公告)号：US20140089682A1

    公开(公告)日：2014-03-27

    申请号：US13626566

    申请日：2012-09-25

    Applicant: APPLE INC.

    Inventor： Manu Gulati ,  Michael J. Smith ,  Shu-Yi Yu

    IPC: G06F21/00

    CPC classification number: G06F21/72 ,  G06F21/575

    Abstract: An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access to the SEP may be strictly controlled by hardware. For example, a mechanism in which the CPUs/APs can only access a mailbox location in the SEP is described. The CPU/AP may write a message to the mailbox, which the SEP may read and respond to. The SEP may include one or more of the following in some embodiments: secure key management using wrapping keys, SEP control of boot and/or power management, and separate trust zones in memory.

    Abstract translation: SOC实现安全飞地处理器（SEP）。 SEP可以包括处理器和一个或多个安全外设。 SEP可以与SOC的其余部分隔离（例如SOC中的一个或多个中央处理单元（CPU），或SOC中的应用处理器（AP））。 对SEP的访问可以由硬件严格控制。 例如，描述了CPU / AP仅能访问SEP中的邮箱位置的机制。 CPU / AP可以向邮箱写入消息，SEP可以读取并响应。 在一些实施例中，SEP可以包括以下一个或多个：使用包装密钥的安全密钥管理，引导和/或电源管理的SEP控制以及存储器中的单独的信任区域。

    Method and apparatus for ensuring real-time snoop latency
    54.
    发明授权
    Method and apparatus for ensuring real-time snoop latency 有权

    公开(公告)号：US10795818B1

    公开(公告)日：2020-10-06

    申请号：US16418811

    申请日：2019-05-21

    Applicant: Apple Inc.

    Inventor： Harshavardhan Kaushikkar ,  Per H. Hammarlund ,  Brian P. Lilly ,  Michael Bekerman ,  James Vash ,  Manu Gulati ,  Benjamin K. Dodge

    IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/0817

    Abstract: Various systems and methods for ensuring real-time snoop latency are disclosed. A system includes a processor and a cache controller. The cache controller receives, via a channel, cache snoop requests from the processor, the snoop requests including latency-sensitive and non-latency sensitive requests. Requests are not prioritized by type within the channel. The cache controller limits a number of non-latency sensitive snoop requests that can be processed ahead of an incoming latency-sensitive snoop requests. Limiting the number of non-latency sensitive snoop requests that can be processed ahead of an incoming latency-sensitive snoop request includes the cache controller determining that the number of received non-latency sensitive snoop requests has reached a predetermined value and responsively prioritizing latency-sensitive requests over non-latency sensitive requests.

    Always-on audio control for mobile device
    55.
    发明授权
    Always-on audio control for mobile device 有权

    公开(公告)号：US10431224B1

    公开(公告)日：2019-10-01

    申请号：US16397057

    申请日：2019-04-29

    Applicant: Apple Inc. ,  Diane Culbert

    Inventor： Timothy J. Millet ,  Manu Gulati ,  Michael F. Culbert

    IPC: G10L15/22 ,  G10L15/28 ,  G06F1/3287 ,  G06F1/3228 ,  G06F3/16 ,  G06F1/32 ,  G10L15/08 ,  G10L25/48

    Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

    Clock switching in always-on component
    57.
    发明授权
    Clock switching in always-on component 有权

    公开(公告)号：US09928838B2

    公开(公告)日：2018-03-27

    申请号：US15482142

    申请日：2017-04-07

    Applicant: Apple Inc.

    Inventor： Manu Gulati ,  Gilbert H. Herbeck ,  Alexei E. Kosut ,  Girault W. Jones ,  Timothy J. Millet

    IPC: G10L15/28 ,  G10L19/00 ,  G10L15/22 ,  G10L15/08

    CPC classification number: G10L15/28 ,  G10L15/08 ,  G10L15/22 ,  G10L2015/088 ,  G10L2015/223

    Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.

    SYSTEM FOR MANAGING MEMORY DEVICES
    58.
    发明申请
    SYSTEM FOR MANAGING MEMORY DEVICES 审中-公开

    公开(公告)号：US20180032281A1

    公开(公告)日：2018-02-01

    申请号：US15225343

    申请日：2016-08-01

    Applicant: Apple Inc.

    Inventor： Manu Gulati ,  Peter F. Holland ,  Erik P. Machnicki ,  Robert E. Jeter ,  Rakesh L. Notani ,  Neeraj Parik ,  Marc A. Schaub

    IPC: G06F3/06 ,  G11C11/406

    CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0683 ,  G06F13/1673 ,  G11C11/40615

    Abstract: In some embodiments, a system includes a memory system, a real-time computing device, and a controller. The real-time computing device stores data within a local buffer having a corresponding storage threshold, where the data satisfies the storage threshold, and where the storage threshold is based on a latency of the memory system and an expected rate of utilization of the data of the local buffer. The controller detects that the memory system should perform an operation, where the memory system is unavailable to the real-time computing device during the operation. In response to detecting that an amount of time for the operation exceeds an amount of time corresponding to the storage threshold, the controller overrides the storage threshold. The controller may override the storage threshold by modifying the storage threshold and by overriding a default priority for access requests of the real-time computing device to the memory system.

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