公开(公告)号：US20230154786A1

公开(公告)日：2023-05-18

申请号：US17527716

申请日：2021-11-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Steven M. Shank ,  Siva P. Adusumilli ,  Alvin Joseph

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76297 ,  H01L21/02595

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure includes a semiconductor substrate having a first trench, and a trench isolation region positioned in the first trench. The trench isolation region contains a dielectric material, the trench isolation region includes a second trench surrounded by the dielectric material, and the trench isolation region includes openings that penetrate through the dielectric material. A semiconductor layer is positioned in the second trench of the trench isolation region. The semiconductor layer contains a single-crystal semiconductor material.

公开(公告)号：US11644620B2

公开(公告)日：2023-05-09

申请号：US17328048

申请日：2021-05-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Steven M. Shank

IPC: G02B6/27 ,  G02B6/126 ,  G02B6/122 ,  G02B6/125

CPC classification number: G02B6/126 ,  G02B6/125 ,  G02B6/1228 ,  G02B6/276

Abstract: Structures for a polarization rotator and methods of fabricating a structure for a polarization rotator. The structure includes a substrate, a first waveguide core over the substrate, and a second waveguide core over the substrate. The second waveguide core is positioned proximate to the section of the first waveguide core. The second waveguide core is comprised of a material having a refractive index that is reversibly variable in response to a stimulus.

公开(公告)号：US11639895B2

公开(公告)日：2023-05-02

申请号：US17195887

申请日：2021-03-09

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  John J. Pekarik ,  Yusheng Bian

IPC: G01N21/64 ,  G01N21/85 ,  H01L31/0232 ,  H01L31/12 ,  H01L31/02

Abstract: A “lab on a chip” includes an optofluidic sensor and components to analyze signals from the optofluidic sensor. The optofluidic sensor includes a substrate, a channel at least partially defined by a portion of a layer of first material on the substrate, input and output fluid reservoirs in fluid communication with the channel, at least a first radiation source coupled to the substrate adapted to generate radiation in a direction toward the channel, and at least one photodiode positioned adjacent and below the channel.

公开(公告)号：US20230125886A1

公开(公告)日：2023-04-27

申请号：US17506992

申请日：2021-10-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Venkata N.R. Vanukuru ,  Mark Levy

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/10

Abstract: Structures for a transistor including regions for landing gate contacts and methods of forming a structure for a transistor that includes regions for landing gate contacts. The structure includes a field-effect transistor having a source region, a gate region, a gate with a sidewall, and a gate extension with a section adjoined to the sidewall. The structure further includes a dielectric layer over the field-effect transistor, and a gate contact positioned in the dielectric layer to land on at least the section of the gate extension.

公开(公告)号：US20230114096A1

公开(公告)日：2023-04-13

申请号：US17450186

申请日：2021-10-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Uzma B. Rana ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L29/06 ,  H01Q1/22 ,  H01L29/08

Abstract: An integrated circuit (IC) structure includes an active device over a bulk semiconductor substrate, and an isolation structure around the active device in the bulk semiconductor substrate. The active device includes a semiconductor layer having a center region, a first end region laterally spaced from the center region by a first trench isolation, a second end region laterally spaced from the center region by a second trench isolation, a gate over the center region, and a source/drain region in each of the first and second end regions. The isolation structure includes: a polycrystalline isolation layer under the active device, a third trench isolation around the active device, and a porous semiconductor layer between the first trench isolation and the polycrystalline isolation layer and between the second trench isolation and the polycrystalline isolation layer.

公开(公告)号：US11569405B2

公开(公告)日：2023-01-31

申请号：US16686973

申请日：2019-11-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Vibhor Jain ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  John J. Pekarik

IPC: H01L31/103 ,  H01L31/18 ,  H01L31/028

Abstract: Structures including a photodetector and methods of fabricating such structures. The photodetector is positioned over the top surface of the substrate. The photodetector includes a portion of a semiconductor layer comprised of a semiconductor alloy, a p-type doped region in the portion of the semiconductor layer, and an n-type doped region in the portion of the semiconductor layer. The p-type doped region and the n-type doped region converge along a p-n junction. The portion of the semiconductor layer has a first side and a second side opposite from the first side. The semiconductor alloy has a composition that is laterally graded from the first side to the second side of the portion of the semiconductor layer.

公开(公告)号：US11545549B2

公开(公告)日：2023-01-03

申请号：US17029667

申请日：2020-09-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Siva P. Adusumilli ,  Yves Ngu ,  Michael Zierak

IPC: H01L29/10 ,  H01L27/12 ,  H01L29/04 ,  H01L21/763

Abstract: Body-contacted semiconductor structures and methods of forming a body-contacted semiconductor structure. A semiconductor substrate, which contains of a single-crystal semiconductor material, includes a device region and a plurality of body contact regions each comprised of the single-crystal semiconductor material. A polycrystalline layer and polycrystalline regions are formed in the semiconductor substrate. The polycrystalline regions are positioned between the polycrystalline layer and the device region, and the polycrystalline regions have a laterally-spaced arrangement with a gap between each adjacent pair of the polycrystalline regions. One of the plurality of body contact regions is arranged in the gap between each adjacent pair of the polycrystalline regions.

公开(公告)号：US11545548B1

公开(公告)日：2023-01-03

申请号：US17361848

申请日：2021-06-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Venkata N. R. Vanukuru

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L29/06 ,  H01L27/118 ,  H01L21/762 ,  H01L27/088

Abstract: Structures for a semiconductor device including airgap isolation and methods of forming a semiconductor device structure that includes airgap isolation. The structure includes a trench isolation region, an active region of semiconductor material surrounded by the trench isolation region, and a field-effect transistor including a gate within the active region. The structure further includes a dielectric layer over the field-effect transistor, a first gate contact coupled to the gate, and a second gate contact coupled to the gate. The first and second gate contacts are positioned in the dielectric layer over the active region, and the second gate contact is spaced along a longitudinal axis of the gate from the first gate contact. The structure further includes an airgap including a portion positioned in the dielectric layer over the gate between the first and second gate contacts.

公开(公告)号：US20220416020A1

公开(公告)日：2022-12-29

申请号：US17361848

申请日：2021-06-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Venkata N.R. Vanukuru

IPC: H01L29/06 ,  H01L27/118 ,  H01L27/088 ,  H01L21/762

Abstract: Structures for a semiconductor device including airgap isolation and methods of forming a semiconductor device structure that includes airgap isolation. The structure includes a trench isolation region, an active region of semiconductor material surrounded by the trench isolation region, and a field-effect transistor including a gate within the active region. The structure further includes a dielectric layer over the field-effect transistor, a first gate contact coupled to the gate, and a second gate contact coupled to the gate. The first and second gate contacts are positioned in the dielectric layer over the active region, and the second gate contact is spaced along a longitudinal axis of the gate from the first gate contact. The structure further includes an airgap including a portion positioned in the dielectric layer over the gate between the first and second gate contacts.

公开(公告)号：US20220271116A1

公开(公告)日：2022-08-25

申请号：US17182415

申请日：2021-02-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  Steven M. Shank ,  Yves T. Ngu ,  Mickey H. Yu

IPC: H01L49/02 ,  H01L27/12

Abstract: A resistor includes at least one polysilicon resistor element in a semiconductor substrate with each polysilicon resistor element having a continuous U-shape with a continuous lateral bottom. The resistor may include an insulator within a valley of the U-shape of each polysilicon resistor element. A plurality of polysilicon resistor elements can be sequentially interconnected to create a serpentine polysilicon resistor. The resistor may also include a dopant-including high resistivity (HR) polysilicon layer thereunder to provide electrical isolation from, and better thermal conduction to, for example, a base semiconductor substrate. The resistor can be used in an SOI substrate. A related method is also disclosed.