公开(公告)号：JP2009271870A

公开(公告)日：2009-11-19

申请号：JP2008124053

申请日：2008-05-09

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SHIMIZU SHUICHI ,  KOMATSU HIDEAKI ,  KAJITANI KOICHI

IPC: G06F11/28

CPC classification number: G05B17/02 ,  G05B2219/23446 ,  G05B2219/23455 ,  G05B2219/2637

Abstract: PROBLEM TO BE SOLVED: To efficiently simulate a system having a plurality of different types of ECUs by software. SOLUTION: In this simulation system, respective ECU emulators #1 to #n are speculatively emulated. That is, the respective ECU emulators #1 to #n operate asynchronously with an individual clock and increment the original speculative period. Further, a system scheduler is provided to maintain all speculative periods sent by the respective ECU emulators, and the system scheduler updates the final time. When an ECU emulator receives an external input having a time stamp ahead of its own speculative period, the ECU emulator rewinds its own clock to the past time indicated by the time stamp and reexecutes a task. For this, the ECU emulator stores its own internal state, suitably in its own private memory at least for a certain fixed period. Consequently, the task can be reproduced by setting the internal state corresponding to the rewound time. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：通过软件有效地模拟具有多种不同类型的ECU的系统。 解决方案：在该仿真系统中，各种ECU模拟器＃1至#n被推测式仿真。 也就是说，相应的ECU模拟器＃1至#n与各个时钟异步运行，并增加原始的推测周期。 此外，提供系统调度器以维持由各个ECU仿真器发送的所有推测周期，并且系统调度器更新最终时间。 当ECU模拟器接收到具有在其自己的推测周期之前的时间戳的外部输入时，ECU仿真器将其自己的时钟倒退到由时间标记指示的过去时间并且执行任务。 为此，ECU仿真器至少在一定的固定时间内存储自己的内部状态，适当地在自己的私人内存中。 因此，可以通过设置对应于重绕时间的内部状态来再现任务。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009259051A

公开(公告)日：2009-11-05

申请号：JP2008108254

申请日：2008-04-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SHIMIZU SHUICHI ,  KOMATSU HIDEAKI ,  KAJITANI KOICHI

IPC: G06F11/28

Abstract: PROBLEM TO BE SOLVED: To provide a technology for understanding the internal state of a built-in program such as an ECU and restoring it to a certain internal state.
SOLUTION: In order to specify and/or extract an internal state memory area, the execution flow of a built-in program such as an ECU is analyzed and a control graph is created. An execution path is thereby obtained. Next, data flow analysis of Def/Use is performed for the execution path. The data flow analysis of Def/Use is to obtain all the lists of variables such that referencing (Use) is performed prior to definition (Def). All the lists of variables thus obtained are regarded as the memory area that expresses the internal state. Using the lists thus obtained of the variables expressing the internal state, an input wrapper and an output wrapper are generated and are arranged in front of and behind the analyzed built-in program, respectively. The program with the wrappers thus arranged therein is either complied or assembled into a binary executable program.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种了解内部程序（如ECU）的内部状态并将其恢复到某种内部状态的技术。

解决方案：为了指定和/或提取内部状态存储区域，分析诸如ECU的内置程序的执行流程并创建控制图。 由此获得执行路径。 接下来，对执行路径执行Def / Use的数据流分析。 Def / Use的数据流分析是获取所有变量列表，以便在定义（Def）之前执行引用（Use）。 所获得的变量的所有列表被视为表示内部状态的存储区域。 使用如此获得的表示内部状态的变量的列表，生成输入包装器和输出包装器，并分别布置在分析的内置程序的前面和后面。 具有如此布置在其中的包装器的程序被编译或组装成二进制可执行程序。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2007179161A

公开(公告)日：2007-07-12

申请号：JP2005374821

申请日：2005-12-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KOSEKI SATOSHI ,  SUGANUMA TOSHIO ,  KOMATSU HIDEAKI

IPC: G06F12/00

CPC classification number: G06F17/3041 ,  G06F17/30471 ,  G06F17/30513 ,  Y10S707/99932 ,  Y10S707/99933

Abstract: PROBLEM TO BE SOLVED: To streamline the execution of a program by pre-fetching data necessary to execute it. SOLUTION: A system is provided for causing a computer to execute a recursive access instruction prior to a program subject to pre-fetching. In the system, query instructions to select records satisfying selection conditions from target tables and generate result tables are detected from iterative processing in the program. An initial query instruction to generate an initial table including variable values to be set prior to the start of the iterative processing in the program is generated. A recursive query instruction to generate, by each recursive query corresponding to the sequentially executed iterative processings, the next intermediate table to be referred to in the subsequent iterative processing from the target tables and an intermediate table including the result tables generated by the preceding target query instructions of the iterative processing is next generated. A final query instruction to generate a final table from the intermediate tables sequentially generated by the recursive queries is then generated. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：通过预取执行它所需的数据来简化程序的执行。 解决方案：提供一种系统，用于使计算机在执行预取的程序之前执行递归访问指令。 在系统中，从程序中的迭代处理中检测到从目标表选择满足选择条件的记录和生成结果表的查询指令。 产生包括在程序中的迭代处理开始之前要设置的变量值的初始表的初始查询指令。 一种递归查询指令，用于通过与顺序执行的迭代处理相对应的每个递归查询来生成在目标表的后续迭代处理中要参考的下一个中间表，以及包括由先前目标查询生成的结果表的中间表 接下来生成迭代处理的指令。 然后生成从递归查询顺序生成的中间表生成最终表的最终查询指令。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007048052A

公开(公告)日：2007-02-22

申请号：JP2005232085

申请日：2005-08-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： OBARA MORIMIKI ,  HAYATA YASUHIKO ,  INOUE HIROSHI ,  MORIYAMA TAKAO ,  KOMATSU HIDEAKI

IPC: G06F9/45

CPC classification number: G06F8/45

Abstract: PROBLEM TO BE SOLVED: To run a program efficiently in a new processor for parallel processing, such as a multi-core processor. SOLUTION: A compiler is provided, which optimizes parallel processing. The compiler records the number of execution cores being the number of processor cores for executing a target program. First, the compiler detects dominant paths being candidates for execution paths to be continuously executed by a single processor core in the target program. Next, the compiler selects the number of dominant paths which is not more than the number of execution cores to thereby generate a cluster of tasks to be parallelly or continuously executed by a multi-core processor. Then, the compiler calculates an execution time when the number of processor cores, equal to one or more natural numbers executes the generated cluster about each of the one or more natural numbers which are not greater than the number of the execution cores for each generated cluster. Then, the number of processor cores to be allocated to execute each cluster is selected on the basis of the calculated execution time. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了并行处理的新处理器，例如多核处理器，有效地运行程序。 解决方案：提供了一个优化并行处理的编译器。 编译器将执行核心数作为执行目标程序的处理器核心数量。 首先，编译器检测主路径是目标程序中的单个处理器核心连续执行的执行路径的候选。 接下来，编译器选择不大于执行核心数量的主要路径的数量，从而生成要由多核处理器并行或连续执行的任务簇。 然后，编译器计算当等于一个或多个自然数的处理器核心的数量对于每个生成的集群执行生成的集群时，关于每个生成的集群的执行核心数不大于一个或多个自然数的每一个 。 然后，根据计算出的执行时间来选择要分配用于执行每个集群的处理器核心的数量。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006155525A

公开(公告)日：2006-06-15

申请号：JP2004349008

申请日：2004-12-01

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NAKAIKE TAKUYA ,  KOMATSU HIDEAKI

IPC: G06F9/48 ,  B25B21/00 ,  B25B21/02 ,  B25D9/00 ,  G06F1/32 ,  G06F11/30

CPC classification number: B25B21/00 ,  B25B21/026 ,  H04L67/02 ,  H04L67/322

Abstract: PROBLEM TO BE SOLVED: To bring response time such as that of a web server close to a target value by more few overheads than up to now. SOLUTION: This control unit is a control unit 25 which controls average response time that is from the time when the information processing system receives a processing request until the time when the system replies to the processing request; and the control unit provides a control unit which is provided with a target response time acquiring part 200 which acquires a target response time that is a target value of an average response time, a predicted response time calculation part 230 which calculates a predicted response time that is a predicted value of average response time at the time when standard period set beforehand passes after the operation mode is set to the information processing system at the case in which either of a plurality of operation modes whose processing performance are different each other, and an operation mode setting part 240 which sets the operation mode to the information processing system when a predicted response time calculated by the predicted response time calculation part is under the target response time. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：通过比现在更多的开销，使Web服务器的响应时间接近目标值。 解决方案：该控制单元是控制从信息处理系统接收到处理请求直到系统回复处理请求的时间的平均响应时间的控制单元25。 并且控制单元提供控制单元，该控制单元设置有获取作为平均响应时间的目标值的目标响应时间的目标响应时间获取部200，计算预测响应时间计算部230， 是在其处理性能彼此不同的多种操作模式中的任一种的情况下，在将操作模式设置为信息处理系统之后，预先设定的标准周期的时间的平均响应时间的预测值， 操作模式设定部240，其在由所述预测响应时间计算部计算出的预测响应时间在所述目标响应时间以下时，将操作模式设定为所述信息处理系统。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006134170A

公开(公告)日：2006-05-25

申请号：JP2004324004

申请日：2004-11-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KOCHIYA KIYOKUNI ,  OGASAWARA TAKESHI ,  KOMATSU HIDEAKI

IPC: G06F9/48

CPC classification number: G06F9/46

Abstract: PROBLEM TO BE SOLVED: To more promptly calculate than before the generation frequency of events generated while each central processing unit executes each thread by a thread and by a central processing unit in a system having a plurality of central processing units.
SOLUTION: An information processor has a generation frequency counter counting the generation frequencies of respective events in a plurality of central processing units. The storage region for thread of each thread records the cumulative generation frequency of the events in executing the thread by the central processing unit by associating the thread with each central processing unit. The storage region for thread of each thread records the value of the generation frequency counter in the central processing unit at a point of time starting the execution of the thread by the central processing unit. A difference value obtained by subtracting the frequency when starting the thread from the value of the generation frequency counter of the central processing unit is added to the cumulative generation frequency of the event corresponding to the central processing unit in the storage region for thread of the thread at the time of completing the execution of the thread.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：在每个中央处理单元通过线程执行每个线程的事件的生成频率和具有多个中央处理单元的系统中的中央处理单元之前，更加及时地计算出问题。 解决方案：信息处理器具有对多个中央处理单元中的各个事件的生成频率进行计数的生成频率计数器。 每个线程的线程的存储区域通过将线程与每个中央处理单元相关联来记录由中央处理单元执行线程的事件的累积生成频率。 每个线程的线程的存储区域在由中央处理单元开始执行线程的时间点处记录中央处理单元中的生成频率计数器的值。 通过从中央处理单元的生成频率计数器的值开始线程减去频率而获得的差值被添加到与线程的线程的存储区域中的对应于中央处理单元的事件的累积生成频率 在完成线程的执行时。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005339021A

公开(公告)日：2005-12-08

申请号：JP2004154794

申请日：2004-05-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KAWAHITO MOTOHIRO ,  KOMATSU HIDEAKI

IPC: G06F9/45

CPC classification number: G06F8/4434

Abstract: PROBLEM TO BE SOLVED: To effectively use instructions unique to an architecture.
SOLUTION: A compiler comprises a target subprogram detection part for detecting a subprogram including instructions corresponding to all the instructions included in a pattern to be replaced, from a plurality of subprograms of a target program to be optimized, as a target subprogram to be optimized, an instruction sequence modification part for modifying instructions other than the instructions corresponding to the instructions included in the pattern to be replaced, and instructions different in execution dependency from the pattern to be replaced, in the target subprogram, such that the instructions included in the target subprogram match the pattern to be replaced in dependency, and an instruction sequence replacement part for replacing the target subprogram modified by the instruction sequence modification part with a replacement instruction sequence corresponding to the pattern to be replaced.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：有效使用架构独特的指令。 解决方案：编译器包括目标子程序检测部分，用于从要优化的目标程序的多个子程序中检测包括与要替换的模式中包括的所有指令相对应的指令的子程序作为目标子程序， 被优化的指令序列修改部分，用于在目标子程序中修改与包括在待替换的模式中的指令相对应的指令之外的指令以及与要替换的模式的执行依赖性不同的指令，使得指令包括 在目标子程序中依赖性地匹配要替换的模式，以及指令序列替换部分，用于用与要替换的模式相对应的替换指令序列替换由指令序列修改部分修改的目标子程序。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005078474A

公开(公告)日：2005-03-24

申请号：JP2003309675

申请日：2003-09-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KOSEKI SATOSHI ,  KOMATSU HIDEAKI

IPC: G06F9/45 ,  G06F9/44

CPC classification number: G06F8/441

Abstract: PROBLEM TO BE SOLVED: To provide an optimizing compiler, compiling method, compiler program, and recording medium, capable of efficiently referring to variant values. SOLUTION: This compiler for optimizing a load command of a program comprises: an executable range detecting means for detecting the executable range of the load command, holding the data read out by the load command in a register, and transferring the data to the executing position of the corresponding load command when executing the load command for each of the entire execution paths backward along an execution order from the corresponding load command in the program; a command generating means for generating a pre-load command in the executable range when there is no pre-load command for generating the same data from the same address as the corresponding load command, which is executed prior to the corresponding load command in the executable range for each of the execution paths; and a command replacing means for replacing a command to delete the corresponding load command and to use the data read out by the corresponding load command with a command to use the data read out by the pre-load command. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供能够有效地参考变体值的优化编译器，编译方法，编译程序和记录介质。 解决方案：用于优化程序的加载命令的编译器包括：可执行范围检测装置，用于检测加载命令的可执行范围，将由加载命令读出的数据保存在寄存器中，并将数据传送到 当从程序中的相应加载命令沿着执行顺序向整个执行路径中的每一个执行加载命令时，相应加载命令的执行位置; 命令产生装置，用于当不存在用于从与可执行程序中的相应加载命令之前执行的相应加载命令相同的地址生成相同数据的预加载命令时，在可执行范围内生成预加载命令 每个执行路径的范围; 以及命令替换装置，用于替换用于删除相应的加载命令的命令，并且使用通过相应的加载命令读出的数据具有使用由预加载命令读出的数据的命令。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004280744A

公开(公告)日：2004-10-07

申请号：JP2003074834

申请日：2003-03-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： INAGAKI TATSUSHI ,  KOMATSU HIDEAKI

IPC: G06F9/45

CPC classification number: G06F8/443

Abstract: PROBLEM TO BE SOLVED: To solve the problem that in requiring resisters of a number exceeding an analyzed number, the necessary register number consequently exceeds the register number provided in a computer, operation must be performed by using a memory lower in speed than the registers with poor efficiency.
SOLUTION: This compiler device for optimizing a program comprises an order limitation information acquisition part for acquiring order limitation information determined between a plurality of instructions of the program; an order determination part for successively determining the execution order of executing each instruction based on the order limitation information; a register number analysis part for analyzing the necessary register number that is the number of registers needed in execution of the instructions with determined execution orders; an instruction detection part for detecting a combination of two instructions, one order being an order-determined instruction, and the other order being an order non-determined instruction, in which an order limitation for executing the one instruction prior to the other instruction is not included in the order limitation information; and an order determination reprocessing part for changing, when the necessary register number exceeds a predetermined number, the one instruction to a state where no execution order is determined and determining the execution orders so as to execute the one command after the other command.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2004272826A

公开(公告)日：2004-09-30

申请号：JP2003066010

申请日：2003-03-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： YASUE TOSHIAKI ,  SUGANUMA TOSHIO ,  KOMATSU HIDEAKI

IPC: G06F9/45

CPC classification number: G06F8/443

Abstract: PROBLEM TO BE SOLVED: To provide a compiler system which eliminates the trouble of requiring a long collection processing time even though the number of times for performing an execution path is appropriately collected, a compiler program, a recording medium, a compiling method, an execution time information generating device and an execution time information generation program. SOLUTION: This compiler system 10 for optimizing a program on the basis of the frequency at which each processing in a program of an optimization object is carried out is provided with a loop processing detecting part 110 for detecting the repeatedly executed loop processing in the program, a loop processing frequency collecting part 140 for collecting a loop processing frequency at which the loop processing is carried out in the program, an intra-loop processings frequency collecting part 150 for collecting an intra-loop processing frequency being a frequency at which a plurality of intra-loop processings included in the loop processing are respectively carried out with respect to the number of times when the loop processing is carried out, an intra-loop execution information generating part 160 for generating intra-loop execution information showing a frequency at which the plurality of intra-loop processings are respectively carried out when the program is performed on the basis of the loop processing frequency and the intra-loop processing frequency, and an optimizing part for optimizing the program on the basis of the intra-loop exectuion information. A frequency in which each processing of the program is carried out can be collected at a high speed. COPYRIGHT: (C)2004,JPO&NCIPI