公开(公告)号：WO2006044349A9

公开(公告)日：2007-08-16

申请号：PCT/US2005036471

申请日：2005-10-11

Applicant: IBM ,  ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L29/04 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: A planar substrate device (100) integrated with fin field effect transistors (FinFETs) and a method of manufâcture comprises a silicon-on-insulator (SOI) wafer (101) comprising a substrate (103); a buried insulator layer (105) over the substrate (103); and a semiconductor layer (115) over the buried insulator layer (105). The structure (100) further comprises a FinFET (130) over the buried insulator layer (105) and a field effect transistor (FET) (131) integrated in the substrate (103), wherein the FET (127) gate is planar to the FinFET gate (125). The structure (100) further comprises retrograde well regions (104, 106, 108, 110) configured in the substrate (103). In one embodiment, the structure (100) further comprises a shallow trench isolation region (111) configured in the substrate (103).

Abstract translation: 与鳍式场效应晶体管（FinFET）集成的平面衬底器件（100）和制造方法包括：包括衬底（103）的绝缘体上硅（SOI）晶片（101）; 衬底（103）之上的掩埋绝缘体层（105）; 和在掩埋绝缘体层（105）上的半导体层（115）。 所述结构（100）还包括在所述掩埋绝缘体层（105）之上的FinFET（130）和集成在所述衬底（103）中的场效应晶体管（FET）（131），其中所述FET（127）栅极与所述 FinFET栅极（125）。 结构（100）还包括配置在衬底（103）中的逆行阱区（104,106,108,110）。 在一个实施例中，结构（100）还包括配置在衬底（103）中的浅沟槽隔离区（111）。

公开(公告)号：WO2005001904A3

公开(公告)日：2005-09-01

申请号：PCT/US2004020552

申请日：2004-06-25

Applicant: IBM ,  ANDERSON BRENT A ,  NOWAK EDWARD J ,  RAINEY BETHANN

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J ,  RAINEY BETHANN

IPC: H01L20060101 ,  H01L21/20 ,  H01L21/324 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/786 ,  H01L31/036

CPC classification number: H01L29/785 ,  H01L21/2022 ,  H01L29/66795

Abstract: A method of providing a freestanding semiconductor layer (26) on a conventional SOI or bulk-substrate silicon device includes forming an amorphous or polycrystalline mandrel (22) on a monocrystalline base structure (20). A conformal polycrystalline semiconductor layer (24) is then formed on the mandrel (22) and on the base structure (20), wherein the polycrystalline layer (24) contacts the base structure (20). The polycrystalline semiconductor layer (24) is then recrystallized so that it has a crystallinity substantially similar to that of the base structure (20). Thus, a freestanding semiconductor layer (26) is formed with a high degree of control of the thickness and height thereof and maintaining a uniformity of thickness.

Abstract translation: 在常规SOI或体硅衬底硅器件上提供独立半导体层（26）的方法包括在单晶基底结构（20）上形成非晶或多晶心轴（22）。 然后在心轴（22）和基底结构（20）上形成共形多晶半导体层（24），其中多晶层（24）接触基底结构（20）。 然后将多晶半导体层（24）重结晶，使其具有与基底结构（20）基本上相似的结晶度。 因此，独立式半导体层（26）以其厚度和高度的高度控制并且保持厚度均匀性形成。

公开(公告)号：WO2005041252A2

公开(公告)日：2005-05-06

申请号：PCT/US2004020907

申请日：2004-06-30

Applicant: IBM ,  CHEN JIA ,  CHAN KEVIN K ,  HUANG SHIH-FEN ,  NOWAK EDWARD J

Inventor： CHEN JIA ,  CHAN KEVIN K ,  HUANG SHIH-FEN ,  NOWAK EDWARD J

IPC: H01L20060101 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/24 ,  H01L29/49 ,  H01L29/76 ,  H01L31/072 ,  H01L31/119 ,  H01L

CPC classification number: H01L21/2807 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/665

Abstract: A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer (41) on the gate dielectric (43). The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe (45) with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer (47), (3) to 4A thick. The thin SiO2 or SixGeyOZ interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of a subsequently deposited layer of cobalt. This gate electrode stack structure is used for both nFETs.and pFETs.

Abstract translation: 在栅极电介质（43）上的硅纳米晶种子层（41）上形成场效应晶体管器件的多层栅电极堆叠结构。 硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积具有高达至少70％的[Ge]的均匀且连续的多晶硅（45）层。 在快速降低的温度下，氧气环境中沉积室的原位吹扫导致薄的SiO 2或SixGeyOz界面层（47），（3）至4A厚。 薄的SiO 2或SixGeyOZ界面层是足够薄且不连续的，以提供对栅极电流的很小的阻力，但是具有足够的[O]以在热处理期间有效地阻挡Ge扩散，从而允许随后沉积的钴的硅化物。 该栅电极堆叠结构用于nFET和pFET。

公开(公告)号：WO2005089440A3

公开(公告)日：2009-04-02

申请号：PCT/US2005008940

申请日：2005-03-18

Applicant: IBM ,  CLARK WILLIAM F JR ,  NOWAK EDWARD J

Inventor： CLARK WILLIAM F JR ,  NOWAK EDWARD J

IPC: H01L27/12 ,  H01L21/336 ,  H01L21/84 ,  H01L29/423 ,  H01L29/786 ,  H01L29/94

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818

Abstract: Disclosed is a method and structure for a fin-type field effect transistor (FinFET) structure that has different thickness gate dielectrics (502, 504) covering the fins (112, 113, 114) extending from the substrate (110). These fins have a central channel region and source (60) and drain (62) regions on opposite sides of the channel region. The thicker gate dielectrics (504) can comprise multiple layers of dielectric (200, 500) and the thinner gate dielectrics (502) can comprise less layers of dielectric (200). A cap (116) comprising a different material than the gate dielectrics can be positioned over the fins.

Abstract translation: 公开了一种鳍式场效应晶体管（FinFET）结构的方法和结构，其具有覆盖从衬底（110）延伸的翅片（112,113,114）的不同厚度的栅极电介质（502,504）。 这些翅片在通道区域的相对侧上具有中心通道区域和源极（60）和漏极（62）区域。 较厚的栅极电介质（504）可以包括多层电介质（200,500），并且较薄的栅极电介质（502）可以包括更少的电介质层（200）。 包括与栅极电介质不同的材料的帽（116）可以位于鳍上。

公开(公告)号：WO2009012276A3

公开(公告)日：2009-03-26

申请号：PCT/US2008070102

申请日：2008-07-16

Applicant: IBM ,  ANDERSON BRENT A ,  BRYANT ANDRES ,  CLARK WILLIAM F ,  NOWAK EDWARD J

Inventor： ANDERSON BRENT A ,  BRYANT ANDRES ,  CLARK WILLIAM F ,  NOWAK EDWARD J

IPC: H01L21/335

CPC classification number: H01L29/78 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7834 ,  H01L29/7835

Abstract: Disclosed are embodiments of an asymmetric field effect transistor structure (200a-c) and a method of forming the structure in which both series resistance in the source region (204, 304) (Rs) and gate (210, 310) to drain ((205, 305) capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay) Specifically, different heights (214, 215) of the source (204) and drain regions (205) and/or different distances (351, 352) between the source (304) and drain regions (305) and the gate (210, 310) are tailored to minimize series resistance in the source region (204, 305) (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate (210, 310) to drain (205, 305) capacitance (i.e., in order to simultaneously ensure that gate ( 210, 310) to drain (205, 305) capacitance is less than a predetermined capacitance value).

Abstract translation: 公开了不对称场效应晶体管结构（200a-c）的实施例以及形成其中源极区（204,304）（Rs）和栅极（210,310）中的两个串联电阻漏极（（ （204）和漏极区域（205）的不同高度（214,215），以便提供最佳性能（即，提供具有最小电路延迟的改进的驱动电流） 和/或源极（304）和漏极区域（305）与栅极（210,310）之间的不同距离（351,352）被调整为使源极区域（204,305）中的串联电阻最小化（即，按顺序 以确保串联电阻小于预定电阻值）并且为了同时使栅极（210,310）与漏极（205,305）的电容最小化（即，为了同时确保栅极（210,310）至 漏极（205,305）电容小于预定电容值）。

公开(公告)号：WO2009012295A3

公开(公告)日：2009-03-12

申请号：PCT/US2008070143

申请日：2008-07-16

Applicant: IBM ,  ANDERSON BRENT A ,  BRYANT ANDRES ,  ELLIS-MONAGHAN JOHN J ,  NOWAK EDWARD J

Inventor： ANDERSON BRENT A ,  BRYANT ANDRES ,  ELLIS-MONAGHAN JOHN J ,  NOWAK EDWARD J

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

Abstract: Disclosed herein are embodiments of a multiple fin fin-type field effect transistor (350) (i.e., a multiple fin dual-gate or tri-gate field effect transistor) (300, 300a, 300b) in which the multiple fins arc partially or completely merged by a highly conductive material (360a, 360b) (e.g., a metal suicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions (375a-b). Merging the semiconductor fins (350) in this manner also allows each of the source/drain regions (375a-b) to be contacted by a single contact via as well as more flexible placement of that contact via.

Abstract translation: 本文公开了多个鳍片式场效应晶体管（350）（即，多鳍式双栅极或三栅极场效应晶体管）（300,300a，300b）的实施例，其中多个鳍片部分地或完全地 由高导电材料（360a，360b）（例如金属硅化物）合并。 以这种方式合并鳍片允许串联电阻最小化，而栅极和源极/漏极区域（375a-b）之间的寄生电容几乎没有增加（如果有的话）。 以这种方式合并半导体鳍（350）还允许每个源极/漏极区（375a-b）通过单个接触通孔接触，以及该接触通孔更灵活的放置。

公开(公告)号：WO2007035788A3

公开(公告)日：2008-11-20

申请号：PCT/US2006036575

申请日：2006-09-19

Applicant: IBM ,  BEINTNER JOCHEN ,  LUDWIG THOMAS ,  NOWAK EDWARD J

Inventor： BEINTNER JOCHEN ,  LUDWIG THOMAS ,  NOWAK EDWARD J

IPC: H01L21/00

CPC classification number: H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

Abstract: A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.

Abstract translation: 用于形成finFET的方法，结构和取向程序。 该方法包括：用第一掩模限定finFET的第一鳍片，并用第二掩模限定finFET的第二鳍片。 该结构包括单晶半导体材料的整体第一和第二鳍片以及第一和第二鳍片的纵向轴线在相同的晶体方向上排列但彼此偏移。 对准过程包括同时将栅极掩模上的对准标记对准由通过用于限定第一鳍片的第一掩模单独形成的对准靶和用于限定第二鳍片的第二掩模。

公开(公告)号：WO2007019023A3

公开(公告)日：2008-11-13

申请号：PCT/US2006028465

申请日：2006-07-21

Applicant: IBM ,  NOWAK EDWARD J

Inventor： NOWAK EDWARD J

IPC: H01L27/108 ,  H01L21/336 ,  H01L29/06 ,  H01L29/76

CPC classification number: H01L29/785 ,  H01L29/66818 ,  H01L29/7856

Abstract: Disclosed herein are improved fin-type field effect transistor (FinFET) structures (100) and the associated methods of manufacturing the structures. In one embodiment FinFET drive current is optimized by configuring the FinFET (100) asymmetrically to decrease fin resistance between the gate (120) and the source region (101 ) and to decrease capacitance between the gate (120) and the drain region (102). In another embodiment device destruction at high voltages is prevented by ballasting the FinFET (300). Specifically, resistance is optimized in the fin (350) between the gate (320) and both the source (301 ) and drain (302) regions (e.g., by increasing fin length (383), by blocking source/drain implant from the fin (350), and by blocking silicide formation on the top surface (395) of the fin) so that the FinFET (300) is operable at a predetermined maximum voltage.

Abstract translation: 本文公开了改进的鳍式场效应晶体管（FinFET）结构（100）以及相关的制造结构的方法。 在一个实施例中，通过非对称地配置FinFET（100）来降低栅极（120）和源极区域（101）之间的鳍电阻并且降低栅极（120）和漏极区域（102）之间的电容来优化FinFET驱动电流。 。 在另一个实施例中，通过对FinFET（300）进行镇流来防止在高电压下的破坏。 具体地说，在栅极（320）和源极（301）和漏极（302）区域之间的鳍片（350）中电阻被优化（例如，通过增加鳍片长度（383），通过从鳍片阻挡源极/漏极注入 （350），并且通过阻挡在鳍的顶表面（395）上的硅化物形成，使得FinFET（300）可在预定的最大电压下操作。

公开(公告)号：WO2008064227A3

公开(公告)日：2008-09-18

申请号：PCT/US2007085246

申请日：2007-11-20

Applicant: IBM ,  ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J

Inventor： ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J

IPC: H01L21/8238

CPC classification number: H01L29/785 ,  H01L21/31155 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1037 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849

Abstract: A semiconductor device (80,85) including semiconductor material (35,40) having a bend and a trench feature formed at the bend, and a gate structure (45,50) at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.

Abstract translation: 一种包括半导体材料（35,40）的半导体器件（80,85），所述半导体材料具有在所述弯曲处形成的弯曲部和沟槽特征以及至少部分地设置在所述沟槽特征中的栅极结构（45,50）。 一种制造半导体结构的方法，包括：在层上形成具有沟槽特征的半导体材料;至少部分地在沟槽特征中形成栅极结构;以及弯曲半导体材料，使得在半导体材料中的反转沟道 栅极结构的区域。

公开(公告)号：WO2011059639A3

公开(公告)日：2011-07-28

申请号：PCT/US2010053091

申请日：2010-10-19

Applicant: IBM ,  ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/28247 ,  H01L21/76834 ,  H01L21/76897

Abstract: The present invention relates generally to semiconductor devices and, more specifically, to damascene gates (100; Fig 1C) having protected shorting regions (60) and related methods for their manufacture. A first aspect of the invention provides a method of forming a damascene gate (100) with protected shorting regions (60), the method comprising: forming a damascene gate having: a gate dielectric atop a substrate (12); a gate conductor (40) atop the gate dielectric; a conductive liner laterally adjacent the gate conductor (30); a spacer between the conductive liner and the substrate (20); and a first dielectric atop the gate conductor (60); removing a portion of the conductive liner (30); and depositing a second dielectric (60) atop a remaining portion of the conductive liner (30), such that the second dielectric is laterally adjacent both the first dielectric and the gate.

Abstract translation: 本发明一般涉及半导体器件，并且更具体地涉及具有受保护的短路区域（60）的镶嵌栅极（100;图1C）以及用于其制造的相关方法。 本发明的第一方面提供一种形成具有受保护的短路区域（60）的镶嵌栅极（100）的方法，所述方法包括：形成镶嵌栅极，所述镶嵌栅极具有：衬底（12）顶上的栅极电介质; 在所述栅极电介质顶上的栅极导体（40） 横向邻近栅极导体（30）的导电衬垫; 导电衬垫和衬底（20）之间的间隔件; 以及在所述栅极导体（60）顶上的第一电介质; 去除导电衬里（30）的一部分; 以及在所述导电衬垫（30）的剩余部分顶上沉积第二电介质（60），使得所述第二电介质横向邻近所述第一电介质和所述栅极。