公开(公告)号：US20250096178A1

公开(公告)日：2025-03-20

申请号：US18969889

申请日：2024-12-05

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Sergio Antonio Chan Arguedas ,  Jimin Yao ,  Chandra Mohan Jha

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/367

Abstract: Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.

公开(公告)号：US12199048B2

公开(公告)日：2025-01-14

申请号：US18397915

申请日：2023-12-27

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ravindranath Mahajan ,  Robert Sankman ,  Shawna Liff ,  Srinivas Pietambaram ,  Bharat Penmecha

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

公开(公告)号：US12142567B2

公开(公告)日：2024-11-12

申请号：US16387167

申请日：2019-04-17

Applicant: Intel Corporation

Inventor： Xiao Di Sun Zhou ,  Debendra Mallik ,  Xiaoying Guo

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31

Abstract: Embodiments include semiconductor packages and method of forming the semiconductor packages. A semiconductor package includes a plurality of conductive layers over a package substrate. The conductive layers include a first conductive layer and first-level interconnects (FLIs) in the package substrate. The semiconductor package also includes a solder resist that surrounds the FLIs, where the solder resist has a top surface that is substantially coplanar to top surfaces of the FLIs, a bridge coupled directly to the first conductive layer with solder balls, where the first conductive layer is coupled to the FLIs, and a dielectric over the conductive layers, the bridge, and the solder resist of the package substrate. The bridge may be an embedded multi-die interconnect bridge (EMIB). The first conductive layer may include first conductive pads and second conductive pads. The FLIs may include first conductive vias, second conductive vias, diffusion layers, and third conductive pads.

公开(公告)号：US20240113087A1

公开(公告)日：2024-04-04

申请号：US17957403

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Brandon Marin ,  Gang Duan ,  Srinivas Pietambaram ,  Suddhasattwa Nad ,  Jeremy Ecton ,  Debendra Mallik ,  Ravindranath Mahajan ,  Rahul Manepalli

IPC: H01L25/10 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/16 ,  H01L23/473 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/105 ,  H01L21/486 ,  H01L23/13 ,  H01L23/16 ,  H01L23/473 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/24 ,  H01L25/18 ,  H01L25/50 ,  H01L24/16 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/16235 ,  H01L2224/24101 ,  H01L2224/24227 ,  H01L2224/73259 ,  H01L2224/92224 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1094

Abstract: An apparatus is provided which comprises: an interposer comprising glass, one or more redistribution layers on a first interposer surface, one or more conductive contacts on a second interposer surface opposite the first interposer surface, one or more vias through the interposer coupling at least one of the conductive contacts on the second interposer surface with the redistribution layers on the first interposer surface, an integrated circuit device embedded within a cavity in the interposer between the first and second interposer surfaces, the embedded integrated circuit device coupled with a first redistribution layers surface, a stack of two or more integrated circuit devices coupled with a second redistribution layers surface opposite the first redistribution layers surface, and mold material surrounding at least one side of the stack of two or more integrated circuit devices. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240063091A1

公开(公告)日：2024-02-22

申请号：US17891735

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Scot Kellar ,  Yoshihiro Tomita ,  Rajiv Mongia ,  Kimin Jun ,  Shawna Liff ,  Wenhao Li ,  Johanna Swan ,  Bhaskar Jyoti Krishnatreya ,  Debendra Mallik ,  Krishna Vasanth Valavala ,  Lei Jiang ,  Xavier Brun ,  Mohammad Enamul Kabir ,  Haris Khan Niazi ,  Jiraporn Seangatith ,  Thomas Sounart

IPC: H01L23/473 ,  H01L23/00 ,  H01L25/065 ,  H01L23/367 ,  H01L23/373

CPC classification number: H01L23/473 ,  H01L24/08 ,  H01L25/0652 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/3677 ,  H01L23/3675 ,  H01L23/3732 ,  H01L23/3738 ,  H01L2924/3511 ,  H01L2224/08145 ,  H01L2224/08121 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/182 ,  H01L2924/186

Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more chiplets bonded to a base die and an inorganic dielectric material adjacent the chiplets and over the base die. The multichip composite device is coupled to a structural member that is made of or includes a heat conducting material, or has integrated fluidic cooling channels to conduct heat from the chiplets and the base die.

公开(公告)号：US20240006332A1

公开(公告)日：2024-01-04

申请号：US17856801

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Dimitrios Antartis ,  Nitin A. Deshpande ,  Siyan Dong ,  Omkar Karhade ,  Gwang-soo Kim ,  Shawna Liff ,  Siddhartha Mal ,  Debendra Mallik ,  Khant Minn ,  Haris Khan Niazi ,  Arnab Sarkar ,  Yi Shi ,  Botao Zhang

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/544 ,  H01L24/08 ,  H01L23/481 ,  H01L2224/08145 ,  H01L2223/54426

Abstract: An integrated circuit (IC) device comprises a host component and an IC die directly bonded to the host component. The IC die comprises a substrate material layer and a die metallization level between the substrate material layer and host component. The IC die includes an upper die alignment fiducial between the die metallization level and host component. The upper die alignment fiducial at least partially overlaps one or more metallization features within the die metallization level. In embodiments, at least two orthogonal edges of the upper die alignment fiducial do not overlap any of the metallization features within the die metallization level. In embodiments, the IC die includes a lower die alignment fiducial between the substrate material layer and the die metallization level. The lower die alignment fiducial may at least partially overlap one or more second metallization features within a second die metallization level of the IC die.

公开(公告)号：US20230420409A1

公开(公告)日：2023-12-28

申请号：US17846086

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Omkar G. Karhade ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Nitin A. Deshpande ,  Pushkar Sharad Ranade ,  Wilfred Gomes ,  Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Joshua Fryman ,  Stephen Morein ,  Matthew Adiletta ,  Michael Crocker ,  Aaron Gorius

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L25/0652 ,  H01L24/08 ,  H01L23/5226 ,  H01L24/94 ,  H01L2224/80896 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L24/97

Abstract: Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; and a second region attached to the first region along a planar interface that is orthogonal to the first surface and parallel to the second surface, the second region having a third surface coplanar with the first surface. The first region comprises: a dielectric material; layers of conductive traces in the dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; conductive vias through the dielectric material; and bond-pads on the first surface, the bond-pads comprising portions of the conductive traces exposed on the first surface, and the second region comprises a material different from the dielectric material.

公开(公告)号：US11798887B2

公开(公告)日：2023-10-24

申请号：US17492476

申请日：2021-10-01

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Tarek Ibrahim ,  Kristof Darmawikarta ,  Rahul N. Manepalli ,  Debendra Mallik ,  Robert L. Sankman

IPC: H01L23/538 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5383 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/09 ,  H01L25/0652

Abstract: A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.

公开(公告)号：US20230299049A1

公开(公告)日：2023-09-21

申请号：US17699028

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： Nitin A. Deshpande ,  Omkar G. Karhade ,  Mohit Bhatia ,  Debendra Mallik

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/16 ,  H01L23/481 ,  H01L24/32 ,  H01L21/76898 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/3128 ,  H01L21/565 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2224/32225 ,  H01L2224/16145 ,  H01L2224/0401

Abstract: A microelectronic component and a method of forming same. The microelectronic component includes: a first substrate having first through vias therein, the first substrate including silicon or glass; a first layer on a front surface of the first substrate and including one or more first dies coupled to the first through vias; a second substrate on a front surface of first layer and having second through vias therein and including silicon or glass; a second layer on a front surface of the second substrate, the first layer between the first substrate and the second substrate, the second layer including one or more second dies coupled to the second through vias; and electrically conductive structures on a back surface of the first substrate coupled to the first through vias.

公开(公告)号：US11756889B2

公开(公告)日：2023-09-12

申请号：US16534027

申请日：2019-08-07

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Kevin McCarthy ,  Leigh M. Tribolet ,  Debendra Mallik ,  Ravindranath V. Mahajan ,  Robert L. Sankman

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/19 ,  H01L24/20 ,  H01L24/80 ,  H01L2221/68354 ,  H01L2221/68372 ,  H01L2224/08225 ,  H01L2224/214 ,  H01L2224/80006 ,  H01L2224/80894 ,  H01L2924/0105 ,  H01L2924/01029 ,  H01L2924/05442

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge with a hybrid layer on a high-density packaging (HDP) substrate, a plurality of dies over the bridge and the HDP substrate, and a plurality of through mold vias (TMVs) on the HDP substrate. The bridge is coupled between the dies and the HDP substrate. The bridge is directly coupled to two dies of the dies with the hybrid layer, where a top surface of the hybrid layer of the bridge is directly on bottom surfaces of the dies, and where a bottom surface of the bridge is directly on a top surface of the HDP substrate. The TMVs couple the HDP substrate to the dies, and have a thickness that is substantially equal to a thickness of the bridge. The hybrid layer includes conductive pads, surface finish, and/or dielectric.