公开(公告)号：US20180300260A1

公开(公告)日：2018-10-18

申请号：US15488840

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Joydeep Ray ,  James A. Valerio ,  Altug Koker ,  Prasoonkumar P. Surti ,  Balaji Vembu ,  Wenyin FU ,  Bhushan M. Borole ,  Kamal Sinha

IPC: G06F12/128 ,  G06F12/0811 ,  G06F13/40 ,  G06T1/20

Abstract: A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.

公开(公告)号：US20180286005A1

公开(公告)日：2018-10-04

申请号：US15477038

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  James A. Valerio ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F9/50

Abstract: One embodiment provides for a general-purpose graphics processing unit comprising a processing array including multiple compute blocks, each compute block including multiple processing clusters and a thread dispatch unit to dispatch threads of a workload to the multiple compute blocks based on a parallelism metric, wherein the thread dispatch unit, based on the parallelism metric, is to perform one of a first operation and a second operation, the first operation to distribute threads across the multiple compute blocks and the second operation is to concentrate threads within one of the multiple compute blocks.

公开(公告)号：US20180285315A1

公开(公告)日：2018-10-04

申请号：US15476987

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  James A. Valerio ,  Altug Koker ,  Abhishek R. Appu ,  Vasanth Ranganathan

IPC: G06F15/80

Abstract: A shared local memory data crossbar may be implemented in multiple stages. With this approach, the number of multiplexer cells can be reduced by fifty percent (50%) or more in some embodiments.