公开(公告)号：US12044888B2

公开(公告)日：2024-07-23

申请号：US17131654

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Xiaoqian Li ,  Nitin Deshpande ,  Sujit Sharan

IPC: G02B6/42

CPC classification number: G02B6/4243 ,  G02B6/423 ,  G02B6/4239

Abstract: A groove alignment structure comprises an etch stop material and a substrate over the etch stop material. A set of grooves is along a first direction in a top surface of the substrate, and adhesive material is in a bottom of the set of grooves. Optical fibers are in the set of grooves over the adhesive material and a portion of the optical fibers extends above the substrate. A set of polymer guides is along the first direction on the top surface of the substrate interleaved with the set of grooves.

公开(公告)号：US12003023B2

公开(公告)日：2024-06-04

申请号：US16258573

申请日：2019-01-26

Applicant: INTEL CORPORATION

Inventor： Zhenguo Jiang ,  Omkar Karhade ,  Srichaitra Chavali ,  Zhichao Zhang ,  Jimin Yao ,  Stephen Smith ,  Xiaoqian Li ,  Robert Sankman

IPC: H01Q1/22 ,  H01L21/56 ,  H01L23/00 ,  H01Q1/38

CPC classification number: H01Q1/38 ,  H01L21/56 ,  H01L24/26 ,  H01Q1/2283 ,  H05K2201/10098

Abstract: An RF chip package comprises a housing and one or more conductive contacts designed to electrically connect the RF chip package to other conductive contacts. The housing includes a first substrate, a 3-D antenna on the first substrate, and a second substrate. The second substrate includes a plurality of semiconductor devices and is bonded to the first substrate. An interconnect structure allows for electrical connection between the first and second substrates. In some cases, the first substrate is flip-chip bonded to the second substrate or is otherwise connected to the second substrate by an array of solder balls. By integrating both the 3-D antenna and RF circuitry together in the same chip package, costs are minimized while bandwidth is greatly improved compared to a separately machined 3-D antenna.

公开(公告)号：US20240120302A1

公开(公告)日：2024-04-11

申请号：US18543749

申请日：2023-12-18

Applicant: Intel Corporation

Inventor： Krishna Bharath Kolluru ,  Atul Maheshwari ,  Mahesh Kumashikar ,  Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Omkar Karhade

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/06 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0655 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/06131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181

Abstract: An electronic device includes first and second external conductive pads coupled to route a first signal and third and fourth external conductive pads. The third and the fourth external conductive pads are between the first and the second external conductive pads on a surface of the electronic device.

公开(公告)号：US20240063072A1

公开(公告)日：2024-02-22

申请号：US17891530

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Shawna Liff ,  Kimin Jun ,  Veronica Strong ,  Aleksandar Aleksov ,  Jiraporn Seangatith ,  Mohammad Enamul Kabir ,  Johanna Swan ,  Tushar Talukdar ,  Omkar Karhade

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L23/29

CPC classification number: H01L23/3135 ,  H01L25/0652 ,  H01L25/0655 ,  H01L23/49816 ,  H01L23/49838 ,  H01L21/568 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/291 ,  H01L24/08

Abstract: Composite integrated circuit (IC) device processing, including selective removal of inorganic dielectric material. Inorganic dielectric material may be deposited, modified with laser exposure, and selectively removed. Laser exposure parameters may be adjusted using surface topography measurements. Inorganic dielectric material removal may reduce surface topography. Vias and trenches of varying size, shape, and depth may be concurrently formed without an etch-stop layer. A composite IC device may include an IC die, a conductive via, and a conductive line adjacent a compositionally homogenous inorganic dielectric material.

公开(公告)号：US20240006358A1

公开(公告)日：2024-01-04

申请号：US17854813

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Zhihua Zou ,  Omkar Karhade ,  Botao Zhang ,  Julia Chiu ,  Vivek Chidambaram ,  Yi Shi ,  Mohit Bhatia ,  Mostafa Aghazadeh

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L2224/08059 ,  H01L2224/08145 ,  H01L2224/80031 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Bonding pedestals on substrates, and their manufacture, for direct bonding integrated circuit (IC) dies onto substrates. The electrical interconnections of one or more IC dies and a substrate are bonded together with the IC dies on and overhanging the pedestals. A bonding pedestal may be formed by etching down the substrate around the interconnections. A system may include one or more such pedestals above and adjacent a recessed surface on a substrate with IC dies overhanging the pedestals. Such a system may be coupled to a host component, such as a board, and a power supply via the host component.

公开(公告)号：US20240006332A1

公开(公告)日：2024-01-04

申请号：US17856801

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Dimitrios Antartis ,  Nitin A. Deshpande ,  Siyan Dong ,  Omkar Karhade ,  Gwang-soo Kim ,  Shawna Liff ,  Siddhartha Mal ,  Debendra Mallik ,  Khant Minn ,  Haris Khan Niazi ,  Arnab Sarkar ,  Yi Shi ,  Botao Zhang

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/544 ,  H01L24/08 ,  H01L23/481 ,  H01L2224/08145 ,  H01L2223/54426

Abstract: An integrated circuit (IC) device comprises a host component and an IC die directly bonded to the host component. The IC die comprises a substrate material layer and a die metallization level between the substrate material layer and host component. The IC die includes an upper die alignment fiducial between the die metallization level and host component. The upper die alignment fiducial at least partially overlaps one or more metallization features within the die metallization level. In embodiments, at least two orthogonal edges of the upper die alignment fiducial do not overlap any of the metallization features within the die metallization level. In embodiments, the IC die includes a lower die alignment fiducial between the substrate material layer and the die metallization level. The lower die alignment fiducial may at least partially overlap one or more second metallization features within a second die metallization level of the IC die.

公开(公告)号：US20230317680A1

公开(公告)日：2023-10-05

申请号：US17707340

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Prabhat Ranjan ,  Boon Ping Koh ,  Min Suet Lim ,  Yew San Lim ,  Ranjul Balakrishnan ,  Omkar Karhade ,  Robert A. Stingel ,  Nitin Deshpande

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/49 ,  H01L24/48 ,  H01L2225/06562 ,  H01L2225/0651 ,  H01L2224/49176 ,  H01L2224/48097 ,  H01L2224/85986

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes one or more ribbon bond connections along with one or more wire bond connections. In one example, ribbon bond connections are shown, and are coupled to ground, and configured to provide a shielding effect to wire bond connections.

公开(公告)号：US11611164B2

公开(公告)日：2023-03-21

申请号：US16454439

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Zhenguo Jiang ,  Omkar Karhade ,  Sri Chaitra Chavali ,  William Lambert ,  Zhichao Zhang ,  Mitul Modi

IPC: H01R12/72 ,  H01R12/77 ,  H01R13/40 ,  H01R13/24 ,  H01R13/6471 ,  H01R107/00

Abstract: A wide bandwidth signal connector plug, comprising a plurality of signal pins having a first anchor portion and a first mating portion, and a plurality of ground pins having a second anchor portion and a second mating portion. The plurality of ground pins is adjacent to the plurality of signal pins. The plurality of signal pins has a first thickness and the plurality of ground pins has a second thickness that is greater than the first thickness. The first anchor portion has a first width and the second anchor portion has a second width that is greater than the first width.

公开(公告)号：US11581240B2

公开(公告)日：2023-02-14

申请号：US16230021

申请日：2018-12-21

Applicant: INTEL CORPORATION

Inventor： Kedar Dhane ,  Omkar Karhade ,  Aravindha R. Antoniswamy ,  Divya Mani

IPC: H01L23/34 ,  H01L23/42 ,  H01L23/31 ,  H01L23/00

Abstract: An integrated circuit package that includes a liquid phase thermal interface material (TIM) is described. The package may include any number of die. The liquid phase TIM can be sealed in a chamber between a die and an integrated heat spreader and bounded on the sides by a perimeter layer. The liquid phase TIM can be fixed in place or circulated, depending on application. A thermal conductivity of the liquid phase TIM can be at least 15 Watts/meter-Kelvin, according to some embodiments. A liquid phase TIM eliminates failure mechanisms present in solid phase TIMs, such as cracking due to warpage and uncontained flow out of the module.

公开(公告)号：US20220399307A1

公开(公告)日：2022-12-15

申请号：US17344681

申请日：2021-06-10

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Sai Vadlamani ,  Omkar Karhade ,  Tolga Acikalin

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/64

Abstract: An electronic substrate may be fabricated having a core comprising a laminate including a metal layer between a first insulator layer and a second insulator layer, a metal via through the core, and metallization features on a first side and a second side of the core, wherein first ones of the metallization features are embedded within dielectric material on the first side of the core, and wherein a sidewall of the dielectric material and of the first insulator layer defines a recess over an area of the metal layer. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.