-
公开(公告)号:US20160173351A1
公开(公告)日:2016-06-16
申请号:US14568789
申请日:2014-12-12
Applicant: Intel Corporation
Inventor: Scott P. Dubal , Patrick Connor , Chris Pavlas
Abstract: One embodiment provides a network adapter. The network adapter includes a network adapter controller, a medium access controller (MAC) and a physical layer (PHY) including at least one port. The network adapter further includes optical communication logic to at least one of receive and/or acquire a local alert and generate a local alert message related to the local alert, the local alert message including an alert identifier (ID) and a network adapter ID. The network adapter further includes a first light emitting diode (LED) to convert the local alert message to a corresponding optical local alert message and to transmit the optical local alert message to an optical communication path.
Abstract translation: 一个实施例提供一种网络适配器。 网络适配器包括网络适配器控制器,媒体接入控制器(MAC)和包括至少一个端口的物理层(PHY)。 网络适配器还包括光通信逻辑,用于接收和/或获取本地警报中的至少一个,并且生成与本地警报相关的本地警报消息,本地警报消息包括警报标识符(ID)和网络适配器ID。 网络适配器还包括第一发光二极管(LED),用于将本地警报消息转换为对应的光学本地警报消息,并将光学本地警报消息发送到光通信路径。
-
公开(公告)号:US20250117673A1
公开(公告)日:2025-04-10
申请号:US18982209
申请日:2024-12-16
Applicant: Intel Corporation
Inventor: Anjali Singhai Jain , Tamar Bar-Kanarik , Marcos Carranza , Karthik Kumar , Cristian Florin Dumitrescu , Keren Guy , Patrick Connor
Abstract: Techniques described herein address the above challenges that arise when using host executed software to manage vector databases by providing a vector database accelerator and shard management offload logic that is implemented within hardware and by software executed on device processors and programmable data planes of a programmable network interface device. In one embodiment, a programmable network interface device includes infrastructure management circuitry configured to facilitate data access for a neural network inference engine having a distributed data model via dynamic management of a node associated with the neural network inference engine, the node including a database shard of a vector database.
-
公开(公告)号:US11960429B2
公开(公告)日:2024-04-16
申请号:US18082485
申请日:2022-12-15
Applicant: Intel Corporation
Inventor: Patrick Connor , Matthew A. Jared , Duke C. Hong , Elizabeth M. Kappler , Chris Pavlas , Scott P. Dubal
CPC classification number: G06F13/4022
Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address. The many-to-many and many-to-one peripheral switches forwards the transaction packets internally within the switch based on the destination address such that the packets are forwarded to a node via which the memory address can be accessed. The platform architectures may also be configured to support migration operations in response to failure or replacement of a node.
-
公开(公告)号:US11797076B2
公开(公告)日:2023-10-24
申请号:US17364523
申请日:2021-06-30
Applicant: Intel Corporation
Inventor: Brian J. Skerry , Ira Weiny , Patrick Connor , Tsung-Yuan C. Tai , Alexander W. Min
IPC: G06F1/3234 , G06F1/3209 , H04L49/00 , H04L49/40
CPC classification number: G06F1/3243 , G06F1/3209 , H04L49/40 , H04L49/70 , Y02D10/00
Abstract: A computer-implemented method can include receiving a queue depth for a receive queue of a network interface controller (NIC), determining whether a power state of a central processing unit (CPU) core mapped to the receive queue should be adjusted based on the queue depth, and adjusting the power state of the CPU core responsive to a determination that the power state of the CPU core should be adjusted.
-
公开(公告)号:US20220114011A1
公开(公告)日:2022-04-14
申请号:US17560231
申请日:2021-12-22
Applicant: Intel Corporation
Inventor: Patrick Connor , Kevin Liedtke , Francesc Guim Bernat , James Hearn
IPC: G06F9/455
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to facilitate network interface device based edge computing. A disclosed example includes threshold analyzer circuitry to identify a resource inactivity threshold for first a resource associated with the network interface device, the resource inactivity threshold indicative of a duration of time that the first resource is not utilized; resource allocator circuitry to determine that the resource meets the resource inactivity threshold; and virtual platform manager circuitry to generate a virtual platform associated with the network interface device based on the determination, the generated virtual platform to reduce latency in execution of a function.
-
公开(公告)号:US20220103185A1
公开(公告)日:2022-03-31
申请号:US17490946
申请日:2021-09-30
Applicant: Intel Corporation
Inventor: Patrick Connor , Kapil Sood , Scott Dubal , Andrew Herdrich , James Hearn
Abstract: Technologies for applying a redundancy encoding scheme to segmented portions of a data block include an endpoint computing device communicatively coupled to a destination computing device. The endpoint computing device is configured to divide a block of data into a plurality of data segments as a function of a transmit window size and a redundancy encoding scheme, and generate redundant data usable to reconstruct each of the plurality of data segments. The endpoint computing device is additionally configured to format a series of network packets that each includes a data segment of the plurality of data segments and generated redundant data for at least one other data segment of the plurality of data segments. Further, the endpoint computing device is configured to transport each of the series of network packets to a destination computing device. Other embodiments are described herein.
-
公开(公告)号:US10601738B2
公开(公告)日:2020-03-24
申请号:US16024774
申请日:2018-06-30
Applicant: Intel Corporation
Inventor: Bruce Richardson , Chris MacNamara , Patrick Fleming , Tomasz Kantecki , Ciara Loftus , John J. Browne , Patrick Connor
IPC: H04L12/861 , H04L12/879
Abstract: Technologies for buffering received network packet data include a compute device with a network interface controller (NIC) configured to determine a packet size of a network packet received by the NIC and identify a preferred buffer size between a small buffer and a large buffer. The NIC is further configured to select, from the descriptor, a buffer pointer based on the preferred buffer size, wherein the buffer pointer comprises one of a small buffer pointer corresponding to a first physical address in memory allocated to the small buffer or a large buffer pointer corresponding to a second physical address in memory allocated to the large buffer. Additionally, the NIC is configured to store at least a portion of the network packet in the memory based on the selected buffer pointer. Other embodiments are described herein.
-
公开(公告)号:US20190103881A1
公开(公告)日:2019-04-04
申请号:US15720400
申请日:2017-09-29
Applicant: Intel Corporation
Inventor: Patrick Connor , Kapil Sood , Scott Dubal , Andrew Herdrich , James Hearn
Abstract: Technologies for applying a redundancy encoding scheme to segmented portions of a data block include an endpoint computing device communicatively coupled to a destination computing device. The endpoint computing device is configured to divide a block of data into a plurality of data segments as a function of a transmit window size and a redundancy encoding scheme, and generate redundant data usable to reconstruct each of the plurality of data segments. The endpoint computing device is additionally configured to format a series of network packets that each includes a data segment of the plurality of data segments and generated redundant data for at least one other data segment of the plurality of data segments. Further, the endpoint computing device is configured to transport each of the series of network packets to a destination computing device. Other embodiments are described herein.
-
59.
公开(公告)号:US20190042297A1
公开(公告)日:2019-02-07
申请号:US16131012
申请日:2018-09-13
Applicant: Intel Corporation
Inventor: Patrick Connor , Scott Dubal , Chris Pavlas , Katalin Bartfai-Walcott , Amritha Nambiar , Sharada Ashok Shiddibhavi
Abstract: Technologies for deploying virtual machines (VMs) in a virtual network function (VNF) infrastructure include a compute device configured to collect a plurality of performance metrics based on a set of key performance indicators, determine a key performance indicator value for each of the set of key performance indicators based on the collected plurality of performance metrics, and determine a service quality index for a virtual machine (VM) instance of a plurality of VM instances managed by the compute as a function each key performance indicator value. Additionally, the compute device is configured to determine whether the determined service quality index is acceptable and perform, in response to a determination that the determined service quality index is not acceptable, an optimization action to ensure the VM instance is deployed on an acceptable host of the compute device. Other embodiments are described herein.
-
60.
公开(公告)号:US20170090987A1
公开(公告)日:2017-03-30
申请号:US14866869
申请日:2015-09-26
Applicant: Intel Corporation
Inventor: James Robert Hearn , Patrick Connor , Kapil Sood , Scott P. Dubal , Andrew J. Herdrich
IPC: G06F9/50 , G06F13/362 , G06F9/48
CPC classification number: G06F9/5011 , G06F9/4881 , G06F9/5027 , G06F13/362 , G06F2209/502 , Y02D10/14 , Y02D10/22
Abstract: In one embodiment, a system comprises platform logic comprising a plurality of processor cores and resource allocation logic. The resource allocation logic may receive a processing request and direct the processing request to a processor core of the plurality of processor cores, wherein the processor core is selected based at least in part on telemetry data associated with the platform logic, the telemetry data indicating a topology of at least a portion of the platform logic.
-
-
-
-
-
-
-
-
-