公开(公告)号：EP3938913A1

公开(公告)日：2022-01-19

申请号：EP20718454.0

申请日：2020-03-14

Applicant: INTEL Corporation

Inventor： KOKER, Altug ,  ASHBAUGH, Ben ,  JANUS, Scott ,  ANANTARAMAN, Aravindh ,  APPU, Abhishek R. ,  COORAY, Niran ,  GEORGE, Varghese ,  HUNTER, Arthur ,  INSKO, Brent ,  OULD-AHMED-VALL, ElMoustapha ,  PANNEER, Selvakumar ,  RANGANATHAN, Vasanth ,  RAY, Joydeep ,  SINHA, Kamal ,  STRIRAMASSARMA, Lakshminarayanan ,  SURTI, Prasoonkumar ,  TANGRI, Saurabh

IPC: G06F12/0804 ,  G06F12/0893 ,  G06F15/173

公开(公告)号：EP3611621A1

公开(公告)日：2020-02-19

申请号：EP19201086.6

申请日：2018-04-17

Applicant: INTEL Corporation

Inventor： KUWAHARA, Atsuo ,  VEMBAR, Deepak S. ,  SAKTHIVEL, Chandrasekaran ,  VENKATARAMAN, Radhakrishnan ,  INSKO, Brent E. ,  KALRA, Anupreet S. ,  LABBE, Hugues ,  APPU, Abhishek R. ,  SHAH, Ankur N. ,  RAY, Joydeep ,  OULD-AHMED-VALL, Elmoustapha ,  SURTI, Prasoonkumar ,  RAMADOSS, Murali

IPC: G06F9/50 ,  G06T15/00

Abstract: A graphics processing engine to process a graphics workload is presented, wherein the graphics processing engine is configured to obtain render tasks from another graphics processing engine and perform one or more of a time warp operation with gaze information or a space warp operation, wherein the time warp operation is a reprojection operation and the space warp operation is a frame rate up conversion operation. The graphics processing engine may comprise a low precision compute engine. The graphics processing engine may also be configured to perform a barrel distortion correction operation. The graphics processing engine may also be implemented in at least one of configurable logic or fixed-functionality logic hardware using circuit technology. The render tasks obtained by the graphics processing engine may be foveated render tasks. The graphics processing engine may be housed in a head-mounted display.

公开(公告)号：EP3608776A1

公开(公告)日：2020-02-12

申请号：EP19183504.0

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： BAUM, Dan ,  ZOHAR, Ronen ,  MISHRA, Asit ,  SURTI, Prasoonkumar ,  ELMOUSTAPHA, Ould-Ahmed-Vall ,  HUGHES, Christopher ,  HEINECKE, Alexander

IPC: G06F9/30

Abstract: Disclosed embodiments relate to apparatuses, systems, and methods for performing sort indexing and/or permutation using an index. An exemplary apparatus includes decode circuitry to decode an instruction, the instruction to include a first field to identify a location of a source vector, a second field to identify a location of a destination vector, and an opcode to indicate to execution circuitry to execute the decoded instruction to sort values of the source vector and store a result of the sort in the destination vector by generating, per each element of the source vector, an index value using one or more comparisons of the element itself and to other data elements of the source vector, and permuting the values of the elements of the source vector based upon the index values for the elements and execution circuitry to execute the decoded instruction as indicated by the opcode.

公开(公告)号：EP3506108A1

公开(公告)日：2019-07-03

申请号：EP18209352.6

申请日：2018-11-29

Applicant: Intel Corporation

Inventor： RAY, Joydeep ,  ASHBAUGH, Ben ,  SURTI, Prasoonkumar ,  RAMANI, Pradeep ,  HARIHARA, Rama ,  JUSTIN, Jerin C. ,  HUANG, Jing ,  CUI, Xiaoming ,  COSTA, Timothy B. ,  GONG, Ting ,  OULD-AHMED-VALL, Elmoustapha ,  BALASUBRAMANIAN, Kumar ,  THOMAS, Anil ,  ELIBOL, Oguz H. ,  BOBBA, Jayaram ,  ZHUANG, Guozhong ,  SUBRAMANIAN, Bhavani ,  KESKIN, Gokce ,  SAKTHIVEL, Chandrasekaran ,  POORNACHANDRAN, Rajesh

IPC: G06F12/02

Abstract: Embodiments are generally directed to compression in machine learning and deep learning processing. An embodiment of an apparatus for compression of untyped data includes a graphical processing unit (GPU) including a data compression pipeline, the data compression pipeline including a data port coupled with one or more shader cores, wherein the data port is to allow transfer of untyped data without format conversion, and a 3D compression/decompression unit to provide for compression of untyped data to be stored to a memory subsystem and decompression of untyped data from the memory subsystem.

公开(公告)号：EP3416135A3

公开(公告)日：2019-03-06

申请号：EP18168352.5

申请日：2018-04-19

Applicant: INTEL Corporation

Inventor： RAY, Joydeep ,  SCHLUESSLER, Travis T. ,  SURTI, Prasoonkumar ,  FEIT, John H. ,  KABURLASOS, Nikos ,  KWIATKOWSKI, Jacek ,  APPU, Abhishek R. ,  HOLLAND, James M. ,  BOLES, Jeffrey S. ,  KENNEDY, Jonathan ,  FENG, Louis ,  KUWAHARA, Atsuo ,  DAS, Barnan ,  BISWAL, Narayan ,  BARAN, Stanley J. ,  CILINGIR, Gokcen ,  SHAH, Nilesh V. ,  SHARMA, Archie ,  VARERKAR, Mayuresh M.

IPC: G06T15/06 ,  H04S7/00

Abstract: Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.

公开(公告)号：EP3401874A1

公开(公告)日：2018-11-14

申请号：EP18159601.6

申请日：2018-03-01

Applicant: INTEL Corporation

Inventor： KOKER, Altug ,  WALD, Ingo ,  PUFFER, David ,  MAIYURAN, Subramaniam M. ,  SURTI, Prasoonkumar ,  VEMBU, Balaji ,  LUEH, Guei-Yuan ,  RAMADOSS, Murali ,  APPU, Abhishek R. ,  RAY, Joydeep

IPC: G06T1/20 ,  G06F9/46 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06T1/20 ,  G06F9/3009 ,  G06F9/30185 ,  G06F9/3851 ,  G06F9/461 ,  G06F9/4843

Abstract: One embodiment provides for a parallel processor comprising a processing array within the parallel processor, the processing array including multiple compute blocks, each compute block including multiple processing clusters configured for parallel operation, wherein each of the multiple compute blocks is independently preemptable. In one embodiment a preemption hint can be generated for source code during compilation to enable a compute unit to determine an efficient point for preemption.

公开(公告)号：EP3396622A1

公开(公告)日：2018-10-31

申请号：EP18159838.4

申请日：2018-03-02

Applicant: INTEL Corporation

Inventor： APPU, Abhishek R. ,  KOKER, Altug ,  WEAST, John C. ,  MACPHERSON, Mike B. ,  HURD, Linda L. ,  BAGHSORKHI, Sara S. ,  GOTTSCHLICH, Justin E. ,  SURTI, Prasoonkumar ,  SAKTHIVEL, Chandrasekaran ,  MA, Liwei ,  OULD-AHMED-VALL, Elmoustapha ,  SINHA, Kamal ,  RAY, Joydeep ,  VEMBU, Balaji ,  JAHAGIRDAR, Sanjeev ,  RANGANATHAN, Vasanth ,  KIM, Dukhwan

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06N3/08

Abstract: A mechanism is described for facilitating inference coordination and processing utilization for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, at training time, information relating to one or more tasks to be performed according to a training dataset relating to a processor including a graphics processor. The method may further include analyzing the information to determine one or more portions of hardware relating to the processor capable of supporting the one or more tasks, and configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks.

公开(公告)号：EP3392873A1

公开(公告)日：2018-10-24

申请号：EP18162140.0

申请日：2018-03-15

Applicant: INTEL Corporation

Inventor： SURTI, Prasoonkumar ,  FU, Wenyin ,  KABURLASOS, Nikos ,  BOROLE, Bhushan M.

IPC: G09G5/10 ,  G09G5/36

CPC classification number: G06F3/04845 ,  G06F2203/04803 ,  G06T1/20 ,  G09G5/10 ,  G09G5/363 ,  G09G2320/0686 ,  G09G2330/021

Abstract: Methods and apparatus relating to techniques for provision of active window rendering optimization and display are described. In an embodiment, a processor is caused to render an active portion of a display device prior to an inactive portion of the display device based at least in part on comparison of a determined size of the active portion of the display device with a threshold value. Furthermore, the active portion of the display device may include a portion of the display device that is being viewed by a user or otherwise a portion of the display device with which a user is interacting. Other embodiments are also disclosed and claimed.

公开(公告)号：EP3392769A1

公开(公告)日：2018-10-24

申请号：EP18167856.6

申请日：2018-04-17

Applicant: INTEL Corporation

Inventor： KUWAHARA, Atsuo ,  VEMBAR, Deepak S. ,  SAKTHIVEL, Chandrasekaran ,  VENKATARAMAN, Radhakrishnan ,  INSKO, Brent E. ,  KALRA, Anupreet S. ,  LABBE, Hugues ,  APPU, Abhishek R. ,  SHAH, Ankur N. ,  RAY, Joydeep ,  OULD-AHMED-VALL, Elmoustapha ,  SURTI, Prasoonkumar ,  RAMADOSS, Murali

IPC: G06F9/50 ,  G06T15/00

CPC classification number: G06T15/005 ,  G06F9/5027 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10 ,  G06T2215/16

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. The second graphics engine may include a low precision compute engine. The system may further include a wearable display housing the second graphics engine. Other embodiments are disclosed and claimed.

公开(公告)号：EP3389018A1

公开(公告)日：2018-10-17

申请号：EP18165260.3

申请日：2018-03-29

Applicant: INTEL Corporation

Inventor： VAIDYANATHAN, Karthik ,  SURTI, Prasoonkumar ,  LABBE, Hugues ,  KUWAHARA, Atsuo ,  KP, Sameer ,  KENNEDY, Jonathan ,  RAMADOSS, Murali ,  APODACA, Michael ,  VENKATESH, Abhishek

IPC: G06T15/00

CPC classification number: G06T11/001 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2210/52

Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.