公开(公告)号：US20190102096A1

公开(公告)日：2019-04-04

申请号：US15721493

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Myron Loewen ,  Sanjeev N. Trika

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0215 ,  G06F12/0246 ,  G06F2212/1028 ,  G06F2212/654 ,  G06F2212/7201

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine prior state information corresponding to one or more of a power state, a system state, a device state, and an operating system state, and load an indirection structure for a persistent storage media in the background based on the prior state information. Other embodiments are disclosed and claimed.

公开(公告)号：US10216415B2

公开(公告)日：2019-02-26

申请号：US15158536

申请日：2016-05-18

Applicant: INTEL CORPORATION

Inventor： Rowel S. Garcia ,  Sanjeev N. Trika

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

Abstract: Provided are a computer program product, system, and method for dynamically increasing capacity of a storage device. For address mappings, each addressing mapping indicates a storage device block address for a host block address and a compressed block size indicating a number of blocks storing compressed data for data written to the host block address starting at the storage device block address. Write data for a write request to a host block address is compressed to produce compressed data. A block size of the compressed data is less than request block size of the write data for the write request. Indication is made in the address mapping for the host block address of a storage device address at which to start storing the compressed data in the storage device and the compressed block size. The compressed data is sent to the storage device to write at the storage device block address.

公开(公告)号：US20190004940A1

公开(公告)日：2019-01-03

申请号：US15637516

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： James A. Boyd ,  John W. Carroll ,  Sanjeev N. Trika

IPC: G06F12/02 ,  G06F13/16 ,  G11C7/10 ,  G06F12/06

CPC classification number: G06F12/0246 ,  G06F12/0623 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/1694 ,  G06F2212/1024 ,  G06F2212/7203 ,  G11C7/1006

Abstract: An embodiment of a memory apparatus may include a persistent host memory buffer, and a memory controller communicatively coupled to the persistent host memory buffer to control communication between the persistent host memory buffer and a persistent storage media device. Other embodiments are disclosed and claimed.

公开(公告)号：US09910786B2

公开(公告)日：2018-03-06

申请号：US14931410

申请日：2015-11-03

Applicant: Intel Corporation

Inventor： James P. Freyensee ,  Sanjeev N. Trika ,  Bryan E. Veal

IPC: G06F11/00 ,  G06F12/10 ,  G06F11/10 ,  G06F11/20

CPC classification number: G06F12/10 ,  G06F11/1076 ,  G06F11/2094 ,  G06F2201/805 ,  G06F2212/1032 ,  G06F2212/1041 ,  G06F2212/205 ,  G06F2212/262 ,  G06F2212/65

Abstract: Disclosed are solutions for resolving a redundant array of independent disks (RAID) write hole, or a parity-based fault scenario that occurs when a power failure and a drive failure occur at or close to the same time. Drive array controller logic assigns a sequence number to write operations received from a computing system and converts respective write operations, including corresponding sequence numbers, to a multiple-drive write to a series of RAID drives. A microcontroller at each drive writes, to a history log (HLOG) on the drive, a logical-to-physical address mapping of a prior sector of the drive that was written along with a corresponding sequence number. Upon receipt of a new write to the mapped logical address, the microcontroller removes the HLOG entry for the logical address, and writes a new entry to the HLOG with a new physical address mapping to the logical address with a new sequence number.

公开(公告)号：US20170220295A1

公开(公告)日：2017-08-03

申请号：US15013183

申请日：2016-02-02

Applicant: Intel Corporation

Inventor： Jawad B. Khan ,  Sanjeev N. Trika ,  Vinodh Gopal ,  Mahesh S. Maddury ,  Omid J. Azizi

IPC: G06F3/06

CPC classification number: G06F3/0652 ,  G06F3/0608 ,  G06F3/0641 ,  G06F3/067 ,  G06F3/0673 ,  G06F3/0685 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/0261 ,  G06F16/1748

Abstract: Technologies for reducing duplication of stored data include storing, by a controller of an apparatus, a first data sub-block of a plurality of data sub-blocks of a data block in a memory at a first physical address. The technologies additionally include storing, by the controller, a pointer in a pointer table. The pointer points to the first physical address. The technologies also include determining, by the controller, whether a second data sub-block of the plurality of data sub-blocks is a duplicate of the first data sub-block, and storing, by the controller in response to a determination that the second data sub-block is a duplicate of the first data sub-block, a second pointer in the pointer table. The second pointer points to the first physical address.

公开(公告)号：US11042323B2

公开(公告)日：2021-06-22

申请号：US16457982

申请日：2019-06-29

Applicant: Intel Corporation

Inventor： Peng Li ,  Jawad B. Khan ,  Sanjeev N. Trika

IPC: G06F3/06 ,  G06F12/1081 ,  G06F12/1009

Abstract: A host-managed storage device includes an offload capability that enables the host to offload all or a portion of a defrag operation to the storage device. Rather than issuing read, write or copy operations and commands to relocate data to the host's DRAM, the host assembles a defrag operation command descriptor for the storage device controller. The command descriptor includes a defrag bitmap that can be directly accessed by the storage device controller to conduct the defrag operation entirely on the storage device at band granularity, without consuming host CPU cycles or host memory. The reduction in host operations/commands achieved by offloading defragmentation to the storage device is on the order of at least a thousand-fold reduction.

公开(公告)号：US20200319815A1

公开(公告)日：2020-10-08

申请号：US16903329

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Bishwajit Dutta ,  Sanjeev N. Trika

IPC: G06F3/06

Abstract: An apparatus comprises a controller comprising an interface comprising circuitry to communicate with a host computing device; and a relocation manager comprising circuitry, the relocation manager to provide, for the host computing device, an identification of a plurality of data blocks to be relocated within a non-volatile memory; and relocate at least a subset of the plurality of data blocks in accordance with a directive provided by the host computing device in response to the identification of the plurality of data blocks to be relocated.

公开(公告)号：US10761779B2

公开(公告)日：2020-09-01

申请号：US16211108

申请日：2018-12-05

Applicant: Intel Corporation

Inventor： Sanjeev N. Trika ,  Steven C. Miller

IPC: G06F12/02 ,  G06F3/06 ,  G06F11/10 ,  H03M13/15

Abstract: Techniques enable offloading operations to be performed closer to where the data is stored in systems with sharded and erasure-coded data, such as in data centers. In one example, a system includes a compute sled or compute node, which includes one or more processors. The system also includes a storage sled or storage node. The storage node includes one or more storage devices. The storage node stores at least one portion of data that is sharded and erasure-coded. Other portions of the data are stored on other storage nodes. The compute node sends a request to offload an operation to the storage node to access the sharded and erasure-coded data. The storage node then sends a request to offload the operation to one or more other storage nodes determined to store one or more codes of the data. The storage nodes perform the operation on the portions of locally stored data and provide the results to the next-level up node.

公开(公告)号：US20200097405A1

公开(公告)日：2020-03-26

申请号：US16585892

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Peng Li ,  Jawad B. Khan ,  Sanjeev N. Trika

IPC: G06F12/06 ,  G11C7/10 ,  G05B19/045

Abstract: An embodiment of a semiconductor package apparatus may include technology to provide a first interface between a first storage device and a host device, and provide a second interface directly between the first storage device and a second storage device. Other embodiments are disclosed and claimed.

公开(公告)号：US10466917B2

公开(公告)日：2019-11-05

申请号：US15721493

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Myron Loewen ,  Sanjeev N. Trika

IPC: G06F3/06 ,  G06F12/02

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine prior state information corresponding to one or more of a power state, a system state, a device state, and an operating system state, and load an indirection structure for a persistent storage media in the background based on the prior state information. Other embodiments are disclosed and claimed.