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    Bypassing error correction code (ECC) processing based on software hint
    52.
    发明授权
    Bypassing error correction code (ECC) processing based on software hint 有权

    公开(公告)号：US11301322B2

    公开(公告)日：2022-04-12

    申请号：US17083256

    申请日：2020-10-28

    Applicant: INTEL CORPORATION

    Inventor： Altug Koker ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray

    IPC: G06F11/10 ,  G11C29/52 ,  G06T15/00 ,  G06T1/60 ,  G06T11/00

    Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive metadata from an application, wherein the meta data indicates one or more processing operations which can accommodate a predetermined level of bit errors in read operations from memory, determine, from the metadata, pixel data for which error correction code bypass is acceptable, and generate one or more error correction code bypass hints for subsequent cache access to the pixel data for which error correction code bypass is acceptable, and transmit the one or more error correction code bypass hints to a graphics processing pipeline. Other embodiments are also disclosed and claimed.

    Apparatus and method for managing data bias in a graphics processing architecture
    53.
    发明授权
    Apparatus and method for managing data bias in a graphics processing architecture 有权

    公开(公告)号：US11282161B2

    公开(公告)日：2022-03-22

    申请号：US16867278

    申请日：2020-05-05

    Applicant: Intel Corporation

    Inventor： Joydeep Ray ,  Abhishek R. Appu ,  Altug Koker ,  Balaji Vembu

    IPC: G06F15/16 ,  G06T1/20 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0888 ,  G06F12/0875 ,  G06T1/60

    Abstract: An apparatus and method are described for managing data which is biased towards a processor or a GPU. For example, an apparatus comprises a processor comprising one or more cores, one or more cache levels, and cache coherence controllers to maintain coherent data in the one or more cache levels; a graphics processing unit (GPU) to execute graphics instructions and process graphics data, wherein the GPU and processor cores are to share a virtual address space for accessing a system memory; a GPU memory addressable through the virtual address space shared by the processor cores and GPU; and bias management circuitry to store an indication for whether the data has a processor bias or a GPU bias, wherein if the data has a GPU bias, the data is to be accessed by the GPU without necessarily accessing the processor's cache coherence controllers.

    Thread scheduling over compute blocks for power optimization
    55.
    发明授权
    Thread scheduling over compute blocks for power optimization 有权

    公开(公告)号：US11227360B2

    公开(公告)日：2022-01-18

    申请号：US16714862

    申请日：2019-12-16

    Applicant: Intel Corporation

    Inventor： Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  James A. Valerio ,  Abhishek R. Appu

    IPC: G06T1/20 ,  G06F9/50

    Abstract: One embodiment provides for a general-purpose graphics processing unit comprising a processing array including multiple compute blocks, each compute block including multiple processing clusters and a thread dispatch unit to dispatch threads of a workload to the multiple compute blocks based on a parallelism metric, wherein the thread dispatch unit, based on the parallelism metric, is to perform one of a first operation and a second operation, the first operation to distribute threads across the multiple compute blocks and the second operation is to concentrate threads within one of the multiple compute blocks.

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