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    Channel estimation using peak cancellation
    53.
    发明授权
    Channel estimation using peak cancellation 有权

    公开(公告)号：US10164800B2

    公开(公告)日：2018-12-25

    申请号：US15475783

    申请日：2017-03-31

    Applicant: Intel Corporation

    Inventor： Albert Molina ,  Kameran Azadet

    IPC: H04L25/02 ,  H04L27/26 ,  H04B7/0413 ,  H04J13/00

    Abstract: An apparatus and a method for estimation a wireless channel are disclosed. For example, the method correlates, by a correlator, a plurality of signals of a combined signal received by a receive antenna over the wireless channel from a plurality of transmit antennas, with respective DMRSs of the plurality of transmit antennas, converts, by a converter, the correlated plurality of signals from frequency to time domain, iteratively peak cancels, by a peak canceller, a largest peak of the combined impulse response and stores a scaling factor and location pair of the cancelled peak until a magnitude of a next largest peak is below a predetermined threshold, assigns, by an assigner, each of the scaling factor and location pairs to a transmit antenna, and estimates, by an estimator, for each of the plurality of transmit antennas, the wireless channel based on the assigned scaling factor and location pairs.

    Devices and methods for pyramid stream encoding
    55.
    发明授权
    Devices and methods for pyramid stream encoding 有权

    公开(公告)号：US09602127B1

    公开(公告)日：2017-03-21

    申请号：US15041326

    申请日：2016-02-11

    Applicant: Intel Corporation

    Inventor： Kameran Azadet

    IPC: H03M7/34 ,  H03M7/38 ,  H03M7/30 ,  H04L29/06

    CPC classification number: H03M7/3082 ,  H03M5/02 ,  H03M7/3066

    Abstract: Devices and methods of reducing quantization noise using a pyramid stream encoder are generally described. Groups of D digital symbols are iteratively computed for a digital signal such that each group of symbols minimizes a norm of a weighted residue vector. The weighted residue vector is formed by applying predetermined weighting coefficients to components of a residue vector. Each component is a difference between a sample of the digital signal and a linear combination of different groups of digital symbols with predefined filter coefficients. The norm of the weighted residue vector evaluated at a rate D times slower than a sampling rate of an output signal. The groups of D digital symbols are provided as the output signal.

    Method and system for digital correction for a dynamically varying non-linear system
    56.
    发明授权
    Method and system for digital correction for a dynamically varying non-linear system 有权

    公开(公告)号：US12273074B2

    公开(公告)日：2025-04-08

    申请号：US17358042

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Kameran Azadet ,  Marc Jan Georges Tiebout ,  Ramon Sanchez ,  Hazar Yuksel

    IPC: H03F1/32 ,  H03F3/21

    Abstract: A system and method for digital correction for a dynamically varying non-linear system. The system includes a correction circuitry including at least one look-up table (LUT). The correction circuitry is configured to receive an input signal and modify the input signal to be processed by the non-linear system using at least one LUT to correct non-linearity incurred by the non-linear system. The at least one LUT is addressed by a magnitude or power of the input signal and a dynamically varying parameter associated with the input signal. The dynamically varying parameter may be one of average signal power of the input signal, a differential of the average power of the input signal, a directional beam index, or temperature.

    Method and apparatus for measuring and cancelling local oscillator feedthrough using an observation receiver
    57.
    发明授权
    Method and apparatus for measuring and cancelling local oscillator feedthrough using an observation receiver 有权

    公开(公告)号：US12261637B2

    公开(公告)日：2025-03-25

    申请号：US17358040

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Kameran Azadet ,  Marc Jan Georges Tiebout

    IPC: H04B1/04 ,  H04L5/12 ,  H04L25/06

    Abstract: A method and apparatus for cancelling local oscillator feedthrough (LOFT). A transmitter includes a first mixer configured to mix a transmit signal with a first local oscillator signal. An observation receiver receives a fraction of a power of the transmit signal as a feedback signal and processes the feedback signal. The observation receiver includes a second mixer configured to mix the feedback signal with a second local oscillator signal. A LOFT correction estimation circuitry is configured to determine a DC offset to cancel LOFT at the first mixer in the transmitter based on measurements on outputs of the second mixer. An LOFT correction circuitry is configured to add the DC offset to the transmit signal. The LOFT correction estimation circuitry may determine the DC offset based on several measurements obtained by varying the DC offset and a phase shift in the second local oscillator signal in the observation receiver.

    Apparatus for correcting a mismatch, digital-to-analog converter system, transmitter, base station, mobile device and method for correcting a mismatch
    59.
    发明授权
    Apparatus for correcting a mismatch, digital-to-analog converter system, transmitter, base station, mobile device and method for correcting a mismatch 有权

    公开(公告)号：US12034450B2

    公开(公告)日：2024-07-09

    申请号：US17754308

    申请日：2019-12-27

    Applicant: Intel Corporation

    Inventor： Daniel Gruber ,  Ramon Sanchez ,  Kameran Azadet ,  Martin Clara

    IPC: H03M1/10 ,  H03M1/06

    CPC classification number: H03M1/1033 ,  H03M1/0626

    Abstract: An apparatus for correcting a mismatch between a first segment and a second segment of a Digital-to-Analog Converter, DAC, is provided. The first segment generates a first contribution to an analog output signal of the DAC based on a first number of bits of a digital input word for the DAC converter, and the second segment generates a second contribution based on a second number of bits. Further, the apparatus comprises a first processing circuit for the first number of bits comprising a first filter configured to modify the first number of bits to generate first modified bits, and a second processing circuit comprising a second filter to modify the second number of bits to generate second modified bits. The apparatus additionally comprises an output configured to output a modified digital input word for the DAC, which is based on the first modified bits and the second modified bits.

    Digital-to-analog converter, digital-to-analog conversion system, electronic system, base station and mobile device
    60.
    发明授权
    Digital-to-analog converter, digital-to-analog conversion system, electronic system, base station and mobile device 有权

    公开(公告)号：US12028090B2

    公开(公告)日：2024-07-02

    申请号：US17754310

    申请日：2019-12-23

    Applicant: Intel Corporation

    Inventor： Albert Molina ,  Kameran Azadet ,  Martin Clara ,  Hundo Shin

    IPC: H03M1/66 ,  H03M1/80

    CPC classification number: H03M1/808

    Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a delay circuit configured to iteratively delay a digital input signal based on a clock signal for generating a plurality of delayed digital input signals. Further, the digital-to-analog converter includes a plurality of groups of inverter cells. Each group of inverter cells is configured to generate a respective analog signal based on one of the plurality of delayed digital input signals. The inverter cells includes a respective inverter circuit configured to invert the respective delayed digital input signal. The plurality of groups of inverter cells include different numbers of inverter cells. The digital-to-analog converter additionally includes an output configured to output an analog output signal based on the analog signals of the plurality of groups of inverter cells.

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