公开(公告)号：US20220116473A1

公开(公告)日：2022-04-14

申请号：US17067690

申请日：2020-10-11

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Daniel Marcovitch ,  Lior Narkis ,  Avi Urman

IPC: H04L29/08

Abstract: A Network-Connected Device (NCD) includes a network interface, a host interface, an NCD memory and an NCD processor. The network interface is configured for communicating over a network. The host interface is configured for communicating with a host. The NCD memory is configured to buffer packet information that originates from the host and pertains to a packet to be transmitted to the network at a specified transmission time. The NCD processor is configured to process the buffered packet information before the specified transmission time, and to transmit the packet to the network at the specified time. Processing of the packet information and transmission of the packet are decoupled from buffering of the packet information.

公开(公告)号：US20220095007A1

公开(公告)日：2022-03-24

申请号：US17542426

申请日：2021-12-05

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan David Levi ,  Michael Kagan

IPC: H04N21/426 ,  G06T1/60

Abstract: Apparatus for data communications includes a host interface, which is configured to be connected to a bus of a host computer having a processor and a memory. Processing circuitry, which is coupled to the host interface, is configured to receive video data with respect to a sequence of pixels, the video data including data words of more than eight bits per pixel for at least one pixel component of the pixels, and to write the video data, via the host interface, to at least one buffer in the memory while justifying the video data in the memory so that the successive pixels in the sequence are byte-aligned in the at least one buffer.

公开(公告)号：US20210235107A1

公开(公告)日：2021-07-29

申请号：US16775463

申请日：2020-01-29

Applicant: Mellanox Technologies, Ltd. ,  BEAMR IMAGING LTD.

Inventor： Dotan David Levi ,  Assaf Weissman ,  Ohad Markus ,  Uri Gadot ,  Aviad Raveh ,  Tamar Shoham

IPC: H04N19/52 ,  H04N19/176 ,  H04N19/177

Abstract: A video processor includes a memory and a processor. The processor is coupled to memory and is configured to store in the memory (i) multiple raw frames belonging to a Group of Pictures (GOP) to be processed, and (ii) one or more reference frames. The processor is further configured to select for multiple target blocks having a same block-location in respective raw frames associated with a common reference frame, a common search region in the common reference frame, and before selecting another search region, to apply at least two motion estimation operations using at least two of the target blocks and the common search region, to estimate respective at least two Motion Vectors (MVs).

公开(公告)号：US20200162234A1

公开(公告)日：2020-05-21

申请号：US16683309

申请日：2019-11-14

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ariel Almog ,  Thomas Kernen ,  Alex Vainman ,  Nir Nitzani ,  Dotan David Levi ,  Ilan Smith ,  Rafi Wiener

IPC: H04L7/10 ,  G06F9/455

Abstract: Apparatus including a shared device in communication with a plurality of computing machines external to the shared device, the shared device including at least one PTP domain coefficient storage area, the at least one PTP domain coefficient storage area receiving a PTP coefficient from a computing machine having a PTP client, and providing the PTP coefficient to a computing machine not having a PTP client. Related apparatus and methods are also provided.

公开(公告)号：US12289389B2

公开(公告)日：2025-04-29

申请号：US18448936

申请日：2023-08-13

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Arnon Sattinger ,  Wojciech Waśko ,  Maciej Machnikowski ,  Doron Fael ,  Ofir Sadeh ,  Jonathan Oliel

IPC: H04L7/033 ,  H03L7/099 ,  H04L7/10

Abstract: In one embodiment, a system includes a digitally controlled oscillator (DCO) to generate a local clock having a local clock frequency, and clock synchronization circuitry to receive from a device a signal indicative of a remote clock frequency, compare measures of the remote clock frequency and the local clock frequency; generate a digital control command based on the comparison; and provide the digital control command to the DCO, wherein the DCO is to adjust the local clock frequency responsively to the digital control command.

公开(公告)号：US20250105938A1

公开(公告)日：2025-03-27

申请号：US18475297

申请日：2023-09-27

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Natan Manevich ,  Dotan David Levi ,  Maciej Machnikowski ,  Wojciech Wasko ,  Elran Abissror ,  Bar Or Shapira ,  Pavel Efros ,  Jonathan Oliel ,  Ofir Sadeh

IPC: H04J3/14 ,  H04J3/06

Abstract: In one embodiment, a monitoring device includes an interface to receive symbols from at least one monitored device over at least one communication link, at least one counter to track a number of the symbols received from the at least one monitored device over the at least one communication link, and processing circuitry to monitor synchronization of at least one clock of the at least one monitored device based on at least one value of the at least one counter.

公开(公告)号：US20250055667A1

公开(公告)日：2025-02-13

申请号：US18420822

申请日：2024-01-24

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Nir Laufer ,  Wojciech Wasko ,  Maciej Machnikowski ,  Doron Fael ,  Arnon Sattinger

IPC: H04L7/00 ,  H04L7/04

Abstract: In one embodiment, a system, includes a digitally controlled oscillator (DCO) to generate a local clock signal having a local clock frequency, and a hardware clock to maintain a value indicative of a local clock time advancing at a frequency proportional to the local clock frequency of the local clock signal generated by the DCO, and clock synchronization circuitry to receive from a device an indication of a remote clock time, generate a digital control command to at least partially correct for a difference between the remote clock time and the local clock time, and provide the digital control command to the DCO, wherein the DCO is to adjust the local clock frequency responsively to the digital control command.

公开(公告)号：US20250036503A1

公开(公告)日：2025-01-30

申请号：US18916370

申请日：2024-10-15

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Shay Aisman ,  Ariel Almog ,  Ran Avraham Koren

IPC: G06F11/07

Abstract: A method includes presenting, by a processing device, in a user interface of a display device, a set of menu items associated with a plurality of criteria and detecting one or more input signals from one or more selections of the set of menu items. The method includes creating a command that includes one or more criteria corresponding to selected options of the plurality of criteria derived from the one or more input signals. The method includes sending, by the processing device, the command to a network adapter device to trigger a polling operation to be performed that causes internal logic of the network adapter device to sample event data associated with a latency of data packets sent by a hardware process that is specific to the one or more criteria.

公开(公告)号：US12158795B2

公开(公告)日：2024-12-03

申请号：US18074751

申请日：2022-12-05

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Shay Aisman ,  Ariel Almog ,  Ran Avraham Koren

IPC: G06F1/04 ,  G06F11/07

Abstract: A device includes a hardware block to perform a hardware process and internal logic coupled between a processing device, which executes instructions, and the hardware block. The internal logic can one of measure execution time or count clock cycles of at least a portion of the hardware process. The internal logic can further, in response to the measured execution time or the counted clock cycles satisfying a predetermined condition, provide data associated with the one of the execution time measurement or the clock cycles count to the processing device, the data being statistically indicative of a latency of data packets sent by the hardware process over a total time the hardware process executes.

公开(公告)号：US20240373379A1

公开(公告)日：2024-11-07

申请号：US18225525

申请日：2023-07-24

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Liron Mula ,  Ariel Almog ,  Bar Shapira ,  Guy Lederman

IPC: H04W56/00

Abstract: A system including an interconnect device coupled with one or more devices where the first device of the one or more devices is to transmit a control block for synchronization via a physical layer of a link coupled to the high-speed interconnect device, the control block comprising a header portion of bits corresponding to a header indicating the block is a control block and a data portion of bits indicating the control block is associated with time synchronization information. The interconnect device is to receive data, parse the data, determine the data is associated with the control block, determine a delay associated with the physical layer transmitting the control block and transmitting a signal responsive to receiving the control block and determining the delay.