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51.发明授权公开(公告)号：US11474748B2
公开(公告)日：2022-10-18
申请号：US17313944
申请日：2021-05-06
Applicant: Micron Technology, Inc.
Inventor： Sivagnanam Parthasarathy , James Fitzpatrick , Patrick Robert Khayat , AbdelHakim S. Alhussien
Abstract: A memory sub-system configured to: measure a plurality of sets of signal and noise characteristics of a group of memory cells in a memory device; determine a plurality of optimized read voltages of the group of memory cells from the plurality of sets of signal and noise characteristics respectively; generate features from the plurality of sets of signal and noise characteristics, including at least one compound feature generated from the plurality of sets of signal and noise characteristics; generate, using the features, a classification of a bit error rate of data retrievable from the group of memory cells; and control an operation to read the group of memory cells based on the classification.
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公开(公告)号：US20220139468A1
公开(公告)日：2022-05-05
申请号：US17577716
申请日：2022-01-18
Applicant: Micron Technology, Inc.
Inventor： James Fitzpatrick , Sivagnanam Parthasarathy , Patrick Robert Khayat , AbdelHakim S. Alhussien
Abstract: A memory sub-system configured to execute a read command of a first type using a combine process to read soft bit data and hard bit data from memory cells. For example, a memory device is to: measure signal and noise characteristics of memory cells for the read command; calculate, based on the characteristics, an optimized voltage and two adjacent voltages that have offsets of a same amount from the optimized voltage; read the memory cells for hard bit data using the optimized voltage and for soft bit data using the two adjacent voltages; and transmit, to the processing device, a response including the hard bit data. The soft bit data can be selectively transmitted based on a classification determined from the characteristics. When a read command of a second type is executed, soft bit data is not read; and/or the signal and noise characteristics are not measured.
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53.发明申请公开(公告)号：US20220107731A1
公开(公告)日：2022-04-07
申请号：US17552179
申请日：2021-12-15
Applicant: Micron Technology, Inc.
Inventor： James Fitzpatrick , Sivagnanam Parthasarathy , Patrick Robert Khayat , AbdelHakim S. Alhussien , Violante Moschiano
Abstract: A memory sub-system configured to improve performance using signal and noise characteristics of memory cells measured during the execution of a command in a memory component. For example, the memory component is enclosed in an integrated circuit and has a calibration circuit. The signal and noise characteristics are measured by the calibration circuit as a byproduct of executing the command in the memory component. A processing device separate from the memory component transmits the command to the memory component, and receives and processes the signal and noise characteristics to identify an attribute about the memory component. Subsequently, an operation related to data stored in the memory component can be performed based on the attribute.
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公开(公告)号：US20220084614A1
公开(公告)日：2022-03-17
申请号：US17536462
申请日：2021-11-29
Applicant: Micron Technology, Inc.
Inventor： Sivagnanam Parthasarathy , James Fitzpatrick , Patrick Robert Khayat , AbdelHakim S. Alhussien
Abstract: A memory sub-system to track charge loss in memory cells and shifts of voltages optimized to read the memory cells. For example, a memory device can measure signal and noise characteristics of a group of memory cells to calculate an optimized read voltage of the group of memory cells. The memory sub-system having the memory device can determine an amount of charge loss in the group of memory cells, using at least the signal and noise characteristics, the optimized read voltage, and/or the bit error rate of data read using the optimized read voltage. The memory sub-system tracks changes in optimized read voltages of memory cells in the memory device based on the amount of charge loss.
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公开(公告)号：US20220084603A1
公开(公告)日：2022-03-17
申请号：US17534885
申请日：2021-11-24
Applicant: Micron Technology, Inc.
Inventor： Patrick Robert Khayat , James Fitzpatrick , AbdelHakim S. Alhussien , Sivagnanam Parthasarathy
Abstract: A memory device to search for a voltage optimized to read a group of memory cells. In response to a read command, the memory device measures first signal and noise characteristics of the memory cells by reading the memory cells at first test voltages. Based on the first signal and noise characteristics, the memory device may determine that the optimized read voltage is outside of a range of the first test voltages. In response, the memory device determines, based on the first signal and noise characteristics, an estimate of the optimized read voltage, and measures second signal and noise characteristics by reading at second test voltages configured around the estimate. The optimized read voltage can be computed based at least in part on the second signal and noise characteristics. The memory device retrieves data from the memory cells using the optimized read voltage.
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Patent Agency Ranking
公开(公告)号：US11257546B2
公开(公告)日：2022-02-22
申请号：US16869488
申请日：2020-05-07
Applicant: Micron Technology, Inc.
Inventor： James Fitzpatrick , Sivagnanam Parthasarathy , Patrick Robert Khayat , AbdelHakim S. Alhussien
Abstract: A memory sub-system configured to execute a read command of a first type using a combine process to read soft bit data and hard bit data from memory cells. For example, a memory device is to: measure signal and noise characteristics of memory cells for the read command; calculate, based on the characteristics, an optimized voltage and two adjacent voltages that have offsets of a same amount from the optimized voltage; read the memory cells for hard bit data using the optimized voltage and for soft bit data using the two adjacent voltages; and transmit, to the processing device, a response including the hard bit data. The soft bit data can be selectively transmitted based on a classification determined from the characteristics. When a read command of a second type is executed, soft bit data is not read; and/or the signal and noise characteristics are not measured.
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公开(公告)号：US11244729B1
公开(公告)日：2022-02-08
申请号：US16988327
申请日：2020-08-07
Applicant: Micron Technology, Inc.
Inventor： Patrick Robert Khayat , James Fitzpatrick , AbdelHakim S. Alhussien , Sivagnanam Parthasarathy
Abstract: A memory device to search for a voltage optimized to read a group of memory cells. In response to a read command, the memory device measures first signal and noise characteristics of the memory cells by reading the memory cells at first test voltages. Based on the first signal and noise characteristics, the memory device may determine that the optimized read voltage is outside of a range of the first test voltages. In response, the memory device determines, based on the first signal and noise characteristics, an estimate of the optimized read voltage, and measures second signal and noise characteristics by reading at second test voltages configured around the estimate. The optimized read voltage can be computed based at least in part on the second signal and noise characteristics. The memory device retrieves data from the memory cells using the optimized read voltage.
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58.发明授权公开(公告)号：US11238953B2
公开(公告)日：2022-02-01
申请号：US16869503
申请日：2020-05-07
Applicant: Micron Technology, Inc.
Inventor： Patrick Robert Khayat , Sivagnanam Parthasarathy , James Fitzpatrick
Abstract: A memory device to estimate a bit error count of data retrievable from a group of memory cells. For example, the memory device has a group of memory cells programmed to store a predetermined number of bits per memory cells to be read at a plurality of first voltages. The memory device determines a plurality of calibrated read voltages corresponding to the plurality of first voltages respectively, based on first signal and noise characteristics of the group of memory cells. The first signal and noise characteristics are used to compute second signal and noise characteristics of the group of memory cells for the calibrated read voltages. The second signal and noise characteristics are used in an empirical formula to compute an estimate of the bit error count of data retrievable from the group of memory cells using the calibrated read voltages.
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公开(公告)号：US20210350869A1
公开(公告)日：2021-11-11
申请号：US17346125
申请日：2021-06-11
Applicant: Micron Technology, Inc.
Inventor： Sivagnanam Parthasarathy , James Fitzpatrick , Patrick Robert Khayat , AbdelHakim S. Alhussien
Abstract: A memory device to generate intelligent, proactive responses to a read command. For example, signal and noise characteristics of a group of memory cells in a memory device are measured to determine a read voltage. An action is identified based on evaluation of the quality of data retrievable using the read voltage from the group of memory cells. While a response indicating the action is provided responsive to the command, the memory device can initiate the action proactively before a subsequent command, following the response, is received.
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公开(公告)号：US20210350866A1
公开(公告)日：2021-11-11
申请号：US16869502
申请日：2020-05-07
Applicant: Micron Technology, Inc.
Inventor： Patrick Robert Khayat , Sivagnanam Parthasarathy , James Fitzpatrick
Abstract: A memory device to estimate signal and noise characteristics of a group of memory cells in response to a command identifying the group of memory cells. For example, the memory device measures first signal and noise characteristics of the group of memory cells based on first test voltages, compute using the first signal and noise characteristics an optimized read voltage of the group of memory cells, and estimate, using the first signal and noise characteristics, second signal and noise characteristics of the group of memory cells, where the second signal and noise characteristics are based on second test voltages that are centered at the optimized read voltage of the group of memory cells.
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