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    ELECTRONIC STILL CAMERA
    54.
    发明专利
    ELECTRONIC STILL CAMERA 失效

    公开(公告)号：JPH11239315A

    公开(公告)日：1999-08-31

    申请号：JP3821598

    申请日：1998-02-20

    Applicant: SONY CORP

    Inventor： MASUDA TAKASHI ,  SHIODA HIROYUKI

    IPC: H04N5/765 ,  H04N5/781 ,  H04N5/91

    Abstract: PROBLEM TO BE SOLVED: To provide an electronic still camera that properly receives data of an image obtained by photographing an object at the point of time when the user is going to photograph it by compensating an inherent delay time based on a shutter speed by the user, a signal processing speed and a signal receiving speed of the camera. SOLUTION: An inherent delay time based on a shutter time of a shutter 8 by the user and a signal processing speed and a receiving speed by the electronic still camera in a delay time detection mode is detected by the operation of the shutter 8 by the user and control of a CPU 10, a photographed signal of an object is received at a prescribed interval from an image pickup element 2 and stored in a 1st storage circuit 11 as, e.g. frame image data. The CPU 10 designates photographed image data corresponding to the detected inherent delay time from the frame photographed image data and the designated data are stored in a 2nd storage circuit 12 as registered photographed image data, and then the inherent delay time detected in the delay time detection mode is compensated and the object is properly photographed without missing the moment for a good picture.

    OPTICAL DATA TRANSMISSION CONNECTOR
    55.
    发明专利
    OPTICAL DATA TRANSMISSION CONNECTOR 失效

    公开(公告)号：JPH09258072A

    公开(公告)日：1997-10-03

    申请号：JP19754796

    申请日：1996-07-26

    Applicant: SONY CORP

    Inventor： KIKUCHI AKIHIRO ,  MASUDA TAKASHI ,  KONDO YOSHIO

    IPC: G02B6/38 ,  G02B6/42 ,  H01L31/0232 ,  H01L33/00 ,  H01L33/58 ,  H01R13/62 ,  H04B10/11 ,  H04B10/116 ,  H04B10/10 ,  H04B10/105 ,  H04B10/22

    Abstract: PROBLEM TO BE SOLVED: To perform sure transmission of a data signal, etc., between equipments having the radio communication function of a data signal, etc., by using an infrared ray. SOLUTION: This device is composed of at least a pair of optical fibers 11, 12; attached/detached to an equipment 30 having a data transmitter/receiver part 30A composed of a light emitting element 36, a light receiving element 37 and a magnetic body; a pair of engaging members 13, supporting the fibers so that their tip parts 19, 20 are located on mutually reverse positions and faced outward and having a stipulating part 18 for prescribing the relative position; and a pair of a magnet member 14, integrally combined with the opposed side faces of the engaging members 13 so that the outer peripheral part of the member 14 is protruded outward. When the engaging state of the engaging members 13 are held by means of the magnetic force of the magnet member 14 relatively engaged with the data transmitter/receiver part 30A, the tip parts 19, 20 of a pair of optical fibers 11, 12 are oppositely located to the light emitting element 36 and the light receiving element 37.

    INTEGRATED CIRCUIT
    59.
    发明专利
    INTEGRATED CIRCUIT 失效

    公开(公告)号：JPS58176725A

    公开(公告)日：1983-10-17

    申请号：JP5866582

    申请日：1982-04-08

    Applicant: SONY CORP

    Inventor： MASUDA TAKASHI ,  KAI KIYOSHI

    IPC: G06F13/14 ,  G06F3/00 ,  G06F13/12 ,  G06F15/78

    Abstract: PURPOSE:To improve the reliability of a logical output IC and to prevent a rise of the cost of an IC, by designating freely a logical output when an output port register of the logical output IC is reset in response to the logical value stored in a memory. CONSTITUTION:Logical values are stored in memory parts 30-3n-1 of a memory 3 in response to a desired logical output obtained when output terminals 80-8n-1 of an output port register 2 are reset. A logical control circuit 4 controls the logical output of the register 2 in accordance with the storage contents of the memory 3 when the circuit 4 is reset after application of a power supply. Therefore flip-flop circuits F0-Fn-1 of the register 2 are set or reset when a reset signal RS' arrives in response to the logical values of storage contents M0-Mn-1 of the memory 3. Then it is possible to designate the logical outputs of output terminals 80-8n-1 of the register 2 at desired levels, respectively.

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