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    MULTIPLEXER CIRCUIT
    51.
    发明专利
    MULTIPLEXER CIRCUIT 失效

    公开(公告)号：JPS63314092A

    公开(公告)日：1988-12-22

    申请号：JP14918987

    申请日：1987-06-17

    Applicant: SONY CORP

    Inventor： KONDOU NORIAKI ,  SASE MASATOSHI

    IPC: H04N9/07 ,  H04N9/78

    Abstract: PURPOSE:To obtain a video signal of less hue deviation by feeding back the output of a comparator, which compares the output signal of a multiplexer circuit with the reference voltage, as the shift level signal to the input side of the multiplexer circuit to shift the DC level of an input signal by a prescribed extent. CONSTITUTION:The variance of the DC component of one color signal outputted from a multiplexer is detected by a comparing circuit 14, and the detection signal is used to shift DC levels of input signals SA and SB in every one horizontal period. The output level of an output OUTA of a switching circuit 13 is monitored and the error voltage is fed back to the input side, where error occurs, of the switching circuit 13. Thus, R and B signals from output terminals OUTA and OUTB are outputted in the same DC level in every horizontal period to resolve a problem that color deviation occurs in every one line of a picture at the time of synthesizing these signals.

    ILLUMINANCE SIGNAL FORMING CIRCUIT
    52.
    发明专利
    ILLUMINANCE SIGNAL FORMING CIRCUIT 失效

    公开(公告)号：JPS63158990A

    公开(公告)日：1988-07-01

    申请号：JP30716886

    申请日：1986-12-23

    Applicant: SONY CORP

    Inventor： SASE MASATOSHI

    IPC: H04N9/07 ,  H04N9/04 ,  H04N9/73

    Abstract: PURPOSE:To obtain illuminance signal whose loopback distortion is controlled of excellent reproducibility and high S/N by forming an illuminance signal by synthesizing a high-band complementary color chrominance color synthesized signal whose level is balanced, with a low-band color signals-synthesized signal. CONSTITUTION:A video signal from a TV camera 2, after subjected to AGC 10, is processed by the specified filter of a color component separation circuit 5, and comes to be color complementary signals W1, YE1, CY1, and their levels are made balanced by a sensitivity correction circuit 6 comprising a color temperature correction circuit 8 and a gain adjustment circuit 7. The signals are then processed by a switched adding circuit 11, and a HPF 12 to come to be level-balanced, and thus a high frequency illuminance signal with which the deterioration of an image signal because of a loopback signal can be evaded is generated. In the meantime, a synthetic illuminance signal whose gain is controlled corresponding to an input of an excellent reproducibility generated jointly by an primary-color conversion circuit 15 to convert respective chrominance signals and output them, a white balance circuit 16, a synthesis circuit 19 to synthesize respective color signals at a prescribed ratio, and a LPF 20, is synthesized with an illuminance signal supplied from a HPF 12. In such a way, an illuminance signal whose is least, reproducibility is excellent and S/N is high is generated.

    AGC CIRCUIT FOR CAMERA
    53.
    发明专利
    AGC CIRCUIT FOR CAMERA 失效

    公开(公告)号：JPS62126776A

    公开(公告)日：1987-06-09

    申请号：JP26637085

    申请日：1985-11-27

    Applicant: SONY CORP

    Inventor： SASE MASATOSHI

    IPC: H04N5/57 ,  H04N5/243

    Abstract: PURPOSE:To give the optimum gain at the part of a picture depending on the part by performing the arithmetic of the optimum gain in each picture element of the picture corresponding to a camera output, and supplying it to a multiplier synchronizing with the output of a memory in which the camera output is stored. CONSTITUTION:An analog signal from an image pickup element inputted from an input terminal 10 is converted to a digital signal at an A/D conversion circuit 11, and is stored at a frame memory 13 through an input/output controller 12. A bit of picture information from the memory 13 is supplied to an arithmetic part 14, the optimum gain required for each part of the picture is operated, and an arithmetic result is written on an address corresponding to the position of the picture of a frame memory 15. And the bit of picture information of the memory 13 is supplied to a multiplier 17 synchronizing with the bit of information of a corresponding memory 15. The output of the multiplier 17 is supplied to a digital signal processing circuit 18, and a luminance signal and two kinds of color difference signals are formed, and are changed to a TV signal at a digital encoder 19.

    Pll circuit
    54.
    发明专利
    Pll circuit 失效
    PLL电路

    公开(公告)号：JPS6159652A

    公开(公告)日：1986-03-27

    申请号：JP17986984

    申请日：1984-08-29

    Applicant: Sony Corp

    Inventor： SASE MASATOSHI

    IPC: G11B15/665 ,  H03L7/099

    Abstract: PURPOSE: To use a phase comparing circuit made into a one-chip IC to make switching between a reference signal and a phase synchronizing signal of this signal possible by connecting a frequency varying varicap of a variable frequency oscillating circuit to a power source and applying the phase comparison output as a difference of the power source voltage.
    CONSTITUTION: The cathode side of a varicap 66 of a variable frequency oscillating circuit 60 having an oscillation center frequency 4fSC is connected to a power supply terminal 67, and an output VL of a phase comparing circuit 20 is supplied to the connection point between the anode and a capacitor 64 through an LPF40. The oscillated output of the circuit 60 is supplied to a terminal B of a comparator 23 through a terminal 20b of the circuit 20 and an 1/N frequency dividing circuit 22, and the output of a quartz oscillating circuit 70 having an oscillation frequency 4fCK is supplied to a terminal A through a terminal 20a and a 1/M frequency dividing circuit 21. The output signal of the circuit 60 is supplied to a frequency dividing circuit 81 to obtain a subcarrier SC having a frequency fSC, and the output signal of the circuit 70 is supplied to a frequency dividing circuit 82 to obtain a clock CK and horizontal and vertical synchronizing pulses.
    COPYRIGHT: (C)1986,JPO&Japio

    Abstract translation: 目的：使用制成单芯片IC的相位比较电路，通过将可变频率振荡电路的变频变压器连接到电源，使该信号的参考信号和相位同步信号之间进行切换，并施加 相位比较输出作为电源电压的差值。 构成：具有振荡中心频率4fSC的变频振荡电路60的变容二极管66的阴极侧连接到电源端子67，相位比较电路20的输出VL被提供给阳极 以及通过LPF40的电容器64。 电路60的振荡输出通过电路20的端子20b和1 / N分频电路22提供给比较器23的端子B，并且具有振荡频率4fCK的石英振荡电路70的输出为 通过端子20a和1 / M分频电路21提供给端子A.电路60的输出信号被提供给分频电路81，以获得具有频率fSC的子载波SC，并且输出信号 电路70被提供给分频电路82以获得时钟CK和水平和垂直同步脉冲。

    SYNTHESIS METHOD FOR SAMPLING OUTPUT
    55.
    发明专利
    SYNTHESIS METHOD FOR SAMPLING OUTPUT 失效

    公开(公告)号：JPS58100590A

    公开(公告)日：1983-06-15

    申请号：JP19985881

    申请日：1981-12-11

    Applicant: SONY CORP

    Inventor： ONGA MAKOTO ,  SASE MASATOSHI ,  YAMANAKA SEISUKE

    IPC: H04N9/07 ,  G11C27/02 ,  H04N9/04

    Abstract: PURPOSE:To prevent the deterioration in frequency characteristics at high frequency of synthesized output signal due to low pass filter effect, by supplying a plurality of sampling outputs selectively to a common hold capacitor via an analog switch. CONSTITUTION:Sampling output signals YH1, YH2 shifted in phase by 2pi/N mutually are switched with an analog switch 63 and applied to a common hold capacitor 64 selectively for summation and synthesis. That is, the sampling output signals YH1, YH2 are switched at each period splitting a sampling period into two and the result is applied to the capacitor 64.

    AMPLIFIER
    59.
    发明专利
    AMPLIFIER 失效

    公开(公告)号：JPH0879772A

    公开(公告)日：1996-03-22

    申请号：JP20753694

    申请日：1994-08-31

    Applicant: SONY CORP

    Inventor： SASE MASATOSHI

    IPC: H04N5/14 ,  H03G3/20 ,  H04N9/09

    Abstract: PURPOSE: To obtain an amplifier device in which a gain of each amplifier is surely made identical without the need for the correction of a gain control signal for each amplifier. CONSTITUTION: Color signals R, G, B are given to AGC amplifiers 1R, 1G, 1B respectively via the position (b) of changeover switches 11R, 11G, 11B. The changeover switches 11R, 11G, 11B are thrown to the position (a) for horizontal and vertical blanking periods to give a pilot signal PL of a prescribed level to the amplifiers 1R, 1G, 1B. The gain of the amplifier 1G is controlled by a gain control signal GC. The output of the amplifiers 1R, 1G, 1B is fed to pilot signal detection circuits 12R, 12G, 12B. A level of the pilot signal PL is detected by detection circuits 12R, 12G, 12B, compared by comparators 13R, 13B and a comparison error output controls the gain of the amplifiers 1R, 1B to make the level of the pilot signal PL via the amplifiers 1R, 1G, 1B equal. The gain of the amplifiers 1R, 1G, 1B is made automatically identical to each other.

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