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51.发明授权公开(公告)号：US11342031B2
公开(公告)日：2022-05-24
申请号：US17006510
申请日：2020-08-28
Inventor： Marco Pasotti , Dario Livornesi , Roberto Bregoli , Vikas Rana , Abhishek Mittal
Abstract: An integrated circuit includes a memory array and a read voltage regulator that generates read voltages from the memory array. The read voltage regulator includes a replica memory cell and the replica bitline current path. The replica memory cell is a replica of memory cells of the memory array. The replica bitline current path is a replica of current paths associated with deadlines of the memory array. The read voltage regulator generates a read voltage based on the current passed through the replica bitline current path. This read voltage is then supplied to the wordlines of the memory array during a read operation.
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公开(公告)号：US20210234460A1
公开(公告)日：2021-07-29
申请号：US17145107
申请日：2021-01-08
Inventor： Vikas Rana , Marco Pasotti , Fabio De Santis
IPC: H02M3/07
Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.
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公开(公告)号：US11031865B2
公开(公告)日：2021-06-08
申请号：US16911967
申请日：2020-06-25
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana
IPC: H02M3/07
Abstract: A charge pump includes an intermediate node capacitively coupled to receive a first clock signal oscillating between a ground and positive supply voltage, the intermediate node generating a first signal oscillating between a first and second voltage. A level shifting circuit shifts the first signal in response to a second clock signal to generate a second signal oscillating between first and third voltages. A CMOS switching circuit includes a first transistor having a source coupled to an input, a second transistor having a source coupled to an output and a gate coupled to receive the second signal. A common drain of the CMOS switching circuit is capacitively coupled to receive the first clock signal. When positively pumping, the first voltage is twice the second voltage and the third voltage is ground. When negatively pumping, the first and third voltages are of opposite polarity and the second voltage is ground.
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54.发明授权公开(公告)号：US10461636B2
公开(公告)日：2019-10-29
申请号：US16162668
申请日：2018-10-17
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana
IPC: H02M3/07 , G05F1/10 , H03K19/096
Abstract: A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.
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55.发明申请公开(公告)号：US20190123638A1
公开(公告)日：2019-04-25
申请号：US16162668
申请日：2018-10-17
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana
IPC: H02M3/07 , G05F1/10 , H03K19/096
CPC classification number: H02M3/07 , G05F1/10 , H02M2003/078 , H03K19/096
Abstract: A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.
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Patent Agency Ranking
56.发明申请公开(公告)号：US20190028026A1
公开(公告)日：2019-01-24
申请号：US15652748
申请日：2017-07-18
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana , Abhishek Mittal
IPC: H02M3/07
CPC classification number: H02M3/073 , H02M2003/071
Abstract: A charge pump includes boosting circuits cascade coupled between first and second nodes, wherein each boosting circuit is operable in both a positive voltage boosting mode to positively boost voltage and a negative voltage boosting mode to negatively boost voltage. A first switching circuit selectively applies a first voltage to one of the cascaded boosting circuits in response to a first logic state of a periodic enable signal, with the cascaded boosting circuits operating in the positive voltage boosting mode to produce a high positive voltage at the second node. A second switching circuit selectively applies a second voltage to another of the cascaded boosting circuits in response to a second logic state of the periodic enable signal, with the cascaded boosting circuits operating in the negative voltage boosting mode to produce a high negative voltage at the first node. Simultaneous output of the positive and negative voltages is made.
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公开(公告)号：US10049736B2
公开(公告)日：2018-08-14
申请号：US15433795
申请日：2017-02-15
Inventor： Marco Pasotti , Marcella Carissimi , Vikas Rana
Abstract: An integrated circuit includes an array of phase-change memory (PCM) cells, and bitlines coupled to the array of PCM cells. The integrated circuit also includes a first decoder circuit having a respective plurality of transistors having a first conductivity type being coupled together and to a given bitline from among the plurality thereof and configured to inject a program current pulse into a selected PCM cell. In addition, the integrated circuit includes a second decoder circuit having a plurality of transistors having a second conductivity type being coupled together and to the given bitline and configured to discharge the given bitline at an end of the program current pulse.
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公开(公告)号：US09634562B1
公开(公告)日：2017-04-25
申请号：US15177830
申请日：2016-06-09
Inventor： Vikas Rana , Marco Pasotti , Fabio De Santis
CPC classification number: H02M3/073
Abstract: A voltage doubler circuit supports operation in a positive voltage boosting mode to positively boost voltage from a first node to a second node and operation in a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuits receive two clock signals having different high voltage levels. A series of voltage doubler circuit are connected in a charge pump with controllable operation in the first and second modes. A connecting circuit interconnects the first and second nodes of the voltage doubler circuits to provide a first connection path, with a first input voltage, to support the positive voltage boosting mode operation and a second connection path, with a proper input voltage, to support the negative voltage boosting mode. A discharge circuit is provided to discharge the voltage doubler circuits when operation of the charge pump circuit is terminated.
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公开(公告)号：US09613696B1
公开(公告)日：2017-04-04
申请号：US14971345
申请日：2015-12-16
Inventor： Marco Pasotti , Marcella Carissimi , Vikas Rana
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0026 , G11C2013/0078
Abstract: An integrated circuit includes an array of phase-change memory (PCM) cells, and bitlines coupled to the array of PCM cells. The integrated circuit also includes a first decoder circuit having a respective plurality of transistors having a first conductivity type being coupled together and to a given bitline from among the plurality thereof and configured to inject a program current pulse into a selected PCM cell. In addition, the integrated circuit includes a second decoder circuit having a plurality of transistors having a second conductivity type being coupled together and to the given bitline and configured to discharge the given bitline at an end of the program current pulse.
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公开(公告)号：US20170047909A1
公开(公告)日：2017-02-16
申请号：US14826017
申请日：2015-08-13
Inventor： Vikas Rana , Fabio De Santis
IPC: H03K3/012 , H03K17/687
CPC classification number: H03K17/102
Abstract: A cascode voltage generating circuit and method are provided. The circuit includes four switching elements. In a high voltage operation mode, the first and second switching elements, respectively, couple a first intermediate voltage input node to a first intermediate voltage output node, and a second intermediate voltage input node to a second intermediate voltage output node. In a low voltage operation mode, the third switching element couples the first and second intermediate voltage input nodes to a ground reference voltage level, and the fourth switching element couples the first and second intermediate voltage output nodes to a supply voltage level.
Abstract translation: 提供了共源共栅电压发生电路和方法。 该电路包括四个开关元件。 在高电压运行模式中，第一和第二开关元件分别将第一中间电压输入节点耦合到第一中间电压输出节点，将第二中间电压输入节点耦合到第二中间电压输出节点。 在低电压操作模式中，第三开关元件将第一和第二中间电压输入节点耦合到接地参考电压电平，第四开关元件将第一和第二中间电压输出节点耦合到电源电压电平。
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