公开(公告)号：US20230039722A1

公开(公告)日：2023-02-09

申请号：US17694011

申请日：2022-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doyoung CHOI ,  Daewon Ha ,  Kyungho Kim ,  Mingyu Kim ,  Kyuman Hwang

IPC: H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes: a substrate including first and second regions, first and second active patterns in the first and second regions, respectively; first source/drain patterns and a first channel pattern including first semiconductor patterns; second source/drain patterns and a second channel pattern including second semiconductor patterns; first and second gate electrodes on the first and second channel patterns, respectively; and a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer includes a first interface layer between the first channel pattern and the first gate electrode, and a first high-k dielectric layer. The second gate dielectric layer includes a second interface layer and a second high-k dielectric layer between the second channel pattern and the second gate electrode. A thickness of the first high-k dielectric layer is greater than that of the second high-k dielectric layer. A thickness of the first semiconductor pattern is less than that of the second semiconductor pattern

公开(公告)号：US20220293595A1

公开(公告)日：2022-09-15

申请号：US17494071

申请日：2021-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin Kim ,  Daewon Ha

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/417

Abstract: An integrated circuit device according to the inventive concept includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a stopper layer that is above and spaced apart from the fin-type active area; a gate electrode extending in a second horizontal direction orthogonal to the first horizontal direction, on the fin-type active area, and in a space between the fin-type active area and the stopper layer; and a gate capping layer on upper surfaces of the gate electrode and the stopper layer.

公开(公告)号：US20220181323A1

公开(公告)日：2022-06-09

申请号：US17394580

申请日：2021-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon Kim ,  Mingyu Kim ,  Doyoung Choi ,  Daewon Ha

IPC: H01L27/092

Abstract: A semiconductor device is disclosed. The semiconductor device may include an active pattern on a substrate, source/drain patterns on the active pattern, a fence spacer on side surfaces of each of the source/drain patterns, a channel pattern interposed between the source/drain patterns, a gate electrode crossing the channel pattern and extending in a first direction, and a gate spacer on a side surface of the gate electrode. A first thickness of an upper portion of the fence spacer in the first direction may be greater than a second thickness of the gate spacer in a second direction crossing the first direction.

公开(公告)号：US11282839B2

公开(公告)日：2022-03-22

申请号：US16870135

申请日：2020-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungmin Kim ,  Daewon Ha

IPC: H01L27/092 ,  H01L29/08 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L23/522 ,  H01L21/02

Abstract: A semiconductor device includes an arrive pattern including a channel region. The channel region is disposed between first and second source/drain patterns that are spaced apart from each other in a first direction. The channel region is configured to connect the first and second source/drain patterns to each other. A gate electrode is disposed on a bottom surface of the active pattern and is disposed between the first and second source/drain patterns. An upper interconnection line is disposed on a top surface of the active pattern opposite to the bottom surface of the active pattern and is connoted to the first source/drain pattern.

公开(公告)号：US10361310B2

公开(公告)日：2019-07-23

申请号：US15463187

申请日：2017-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daewon Ha ,  Seungseok Ha ,  Byoung Hak Hong

IPC: H01L29/41 ,  H01L29/78 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, removing the sacrificial gate pattern to form a gap region exposing the active fin, and forming a separation region in the active fin exposed by the gap region. Forming the separation region includes forming an oxide layer in the exposed active fin and forming an impurity regions with impurities implanted into the exposed active fin.

公开(公告)号：US09431522B2

公开(公告)日：2016-08-30

申请号：US15003288

申请日：2016-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin Kim ,  Sung-Dae Suk ,  Jaehoo Park ,  Dongho Cha ,  Daewon Ha

IPC: H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/308 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/02233 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method of manufacturing a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, forming an interlayer insulating layer on the sacrificial gate pattern, removing the sacrificial gate pattern to form a gap region exposing the active fin in the interlayer insulating layer, and oxidizing a portion of the active fin exposed by the gap region to form an insulation pattern between the active fin and the substrate.

公开(公告)号：US20140335673A1

公开(公告)日：2014-11-13

申请号：US14262937

申请日：2014-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNGMIN KIM ,  Sung-Dae Suk ,  Jaehoo Park ,  Dongho Cha ,  Daewon Ha

IPC: H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/02233 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method of manufacturing a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, forming an interlayer insulating layer on the sacrificial gate pattern, removing the sacrificial gate pattern to form a gap region exposing the active fin in the interlayer insulating layer, and oxidizing a portion of the active fin exposed by the gap region to form an insulation pattern between the active fin and the substrate.

Abstract translation: 制造半导体器件的方法包括：图案化衬底以形成有源鳍片，形成与衬底上的有源鳍片交叉的牺牲栅极图案，在牺牲栅极图案上形成层间绝缘层，去除牺牲栅极图案以形成 间隙区域使层间绝缘层中的活性鳍片曝光，并且氧化由间隙区域暴露的活性鳍片的一部分，以在活性鳍片和衬底之间形成绝缘图案。