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    Command execution using existing address information
    51.
    发明授权
    Command execution using existing address information 有权
    使用现有地址信息执行命令

    公开(公告)号：US09026699B2

    公开(公告)日：2015-05-05

    申请号：US14034211

    申请日：2013-09-23

    Applicant: Seagate Technology LLC

    Inventor： Kris Conklin ,  Bruce Dunlop ,  Mark Allen Gaertner ,  Ryan James Goss

    IPC: G06F13/12 ,  G06F13/38 ,  G06F13/28 ,  G06F12/02

    CPC classification number: G06F12/0246 ,  G06F13/161 ,  G06F2212/1016 ,  G06F2212/7203

    Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a plurality of solid-state non-volatile memory cells. A controller communicates a first command having address information and a first operation code. The first operation code identifies a first action to be taken by the memory module in relation to the address information. The controller subsequently communicates a second command having a second operation code without corresponding address information. The memory module takes a second action identified by the second command using the address information from the first command.

    Abstract translation: 用于管理诸如闪存之类的存储器中的数据的方法和装置。 根据一些实施例，存储器模块具有多个固态非易失性存储单元。 控制器传达具有地址信息的第一命令和第一操作码。 第一操作代码识别存储器模块相对于地址信息采取的第一动作。 控制器随后传送具有第二操作码的第二命令，而没有相应的地址信息。 存储器模块使用来自第一命令的地址信息采用由第二命令标识的第二动作。

    TORN WRITE MITIGATION
    52.
    发明申请
    TORN WRITE MITIGATION 有权
    TORN写入缓解

    公开(公告)号：US20150046747A1

    公开(公告)日：2015-02-12

    申请号：US13961755

    申请日：2013-08-07

    Applicant: Seagate Technology LLC

    Inventor： Mark Allen Gaertner ,  Jon Trantham ,  Vidya Krishnamurthy ,  Steve Faulhaber ,  Yong Yang

    IPC: G06F11/16

    CPC classification number: G06F11/1666 ,  G06F11/1441 ,  G06F11/2015

    Abstract: Torn write mitigation circuitry determines if a write operation to memory is in progress at or about a time of power loss. In response to the write operation being in progress at or about the time of the power loss, the torn write mitigation circuitry causes torn write data and metadata to be stored to a non-volatile cache. The torn write data comprise data left in a degraded or uncorrectable state as a result of the loss of power. The metadata describe the torn write data.

    Abstract translation: 被破坏的写入缓冲电路确定在功率损耗时间或约一个时间内对存储器的写入操作是否正在进行。 为了响应于在功率损耗的时间或周围的写入操作，被破坏的写入缓冲电路导致撕裂的写入数据和元数据被存储到非易失性高速缓存。 被破坏的写数据包括由于功率损失而处于劣化或不可校正状态的数据。 元数据描述了被破坏的写入数据。

    FORMING A CHARACTERIZATION PARAMETER OF A RESISTIVE MEMORY ELEMENT
    54.
    发明申请
    FORMING A CHARACTERIZATION PARAMETER OF A RESISTIVE MEMORY ELEMENT 有权
    形成电阻记忆元素的特征参数

    公开(公告)号：US20140258646A1

    公开(公告)日：2014-09-11

    申请号：US13789123

    申请日：2013-03-07

    Applicant: SEAGATE TECHNOLOGY LLC

    Inventor： Ryan James Goss ,  Mark Allen Gaertner ,  Antoine Khoueir ,  David Scott Ebsen ,  Jon D. Trantham

    IPC: G06F12/00

    CPC classification number: G11C29/50008 ,  G06F11/10 ,  G06F11/1012 ,  G11C13/00 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0083 ,  G11C2013/0092

    Abstract: An incremental signal is defined that includes at least one of a duration and a peak voltage that is less than a respective minimum programming time or minimum programming voltage step of a resistive memory element. A characterization procedure is repeatedly performed that at least involves: applying a signal to the memory element, the signal being incremented by the incremental signal during each subsequent application; measuring a first resistance of the memory element in response to the signal; and c) measuring a second resistance of the memory element after a time period has elapsed from the measurement of the first resistance with no programming signal applied. In response to the first and second resistance measurements of the characterization procedure, a characterization parameter of the memory element is formed.

    Abstract translation: 定义增量信号，其包括持续时间和峰值电压中的至少一个小于电阻式存储器元件的相应的最小编程时间或最小编程电压阶跃。 重复执行表征过程，其至少包括：将信号施加到存储元件，在每个随后的应用期间，信号由增量信号递增; 响应于所述信号测量所述存储元件的第一电阻; 以及c）在没有施加编程信号的第一电阻的测量经过一段时间之后测量存储元件的第二电阻。 响应于表征过程的第一和第二电阻测量，形成存储元件的表征参数。

    Metadata Update Management In a Multi-Tiered Memory
    55.
    发明申请
    Metadata Update Management In a Multi-Tiered Memory 审中-公开
    元数据更新管理在多层内存中

    公开(公告)号：US20140244897A1

    公开(公告)日：2014-08-28

    申请号：US13777868

    申请日：2013-02-26

    Applicant: SEAGATE TECHNOLOGY LLC

    Inventor： Ryan James Goss ,  David Scott Ebsen ,  Mark Allen Gaertner

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G06F12/0238 ,  G06F2212/217 ,  G06F2212/7205 ,  G06F2212/7207

    Abstract: Method and apparatus for managing data in a memory. In accordance with some embodiments, metadata updates are stored in a first tier of a a multi-tier non-volatile memory structure responsive to access operations associated with data objects in the memory structure. The stored metadata updates are logged in a second, lower tier of the memory structure. The stored metadata updates are further migrated to a different location within the first tier responsive to an accumulated count of said access operations.

    Abstract translation: 用于管理存储器中的数据的方法和装置。 根据一些实施例，响应于与存储器结构中的数据对象相关联的访问操作，元数据更新被存储在多层非易失性存储器结构的第一层中。 存储的元数据更新记录在内存结构的第二个较低层。 响应于所述访问操作的累积计数，存储的元数据更新进一步迁移到第一层内的不同位置。

    Storing Error Correction Code (ECC) Data In a Multi-Tier Memory Structure
    56.
    发明申请
    Storing Error Correction Code (ECC) Data In a Multi-Tier Memory Structure 审中-公开
    在多层存储器结构中存储纠错码（ECC）数据

    公开(公告)号：US20140229655A1

    公开(公告)日：2014-08-14

    申请号：US13762765

    申请日：2013-02-08

    Applicant: SEAGATE TECHNOLOGY LLC

    Inventor： Ryan James Goss ,  Mark Allen Gaertner ,  Ara Patapoutian

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G06F11/1048 ,  G06F2212/7207

    Abstract: Method and apparatus for managing data in a memory. In accordance with some embodiments, a data object is stored in a first non-volatile tier of a multi-tier memory structure. An ECC data set adapted to detect at least one bit error in the data object during a read operation is generated. The ECC data set is stored in a different, second non-volatile tier of the multi-tier memory structure.

    Abstract translation: 用于管理存储器中的数据的方法和装置。 根据一些实施例，数据对象被存储在多层存储器结构的第一非易失性层中。 生成适于在读取操作期间检测数据对象中的至少一个位错误的ECC数据集。 ECC数据集存储在多层存储器结构的不同的第二非易失性层中。

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