公开(公告)号：US07372066B2

公开(公告)日：2008-05-13

申请号：US10516703

申请日：2003-06-04

Applicant: Hisao Sato ,  Tomoya Sugahara ,  Shinji Kitazawa ,  Yoshihiko Muramoto ,  Shiro Sakai

Inventor： Hisao Sato ,  Tomoya Sugahara ,  Shinji Kitazawa ,  Yoshihiko Muramoto ,  Shiro Sakai

IPC: H01L29/06

CPC classification number: H01L33/32 ,  B82Y20/00 ,  H01L33/04 ,  H01L33/06

Abstract: A light-emitting element using GaN. On a substrate (10), formed are an SiN buffer layer (12), a GaN buffer layer (14), an undoped GaN layer (16), an Si-doped n-GaN layer (18), an SLS layer (20), an undoped GaN layer (22), an MQW light-emitting layer (24), an SLS layer (26), and a p-GaN layer (28), forming a p electrode (30) and an n electrode (32). The MQW light-emitting layer (24) has a structure in which InGaN well layers and AlGaN barrier layers are alternated. The Al content ratios of the SLS layers (20, and 26) are more than 5% and less than 24%. The In content ratio of the well layer in the MQW light-emitting layer (24) is more than 3% and less than 20%. The Al content ratio of the barrier layer is more than 1% and less than 30%. By adjusting the content ratio and film thickness of each layer to a desired value, the light luminous efficiency for wavelength of less than 400 nm is improved.

Abstract translation: 使用GaN的发光元件。 在形成的衬底（10）上形成SiN缓冲层（12），GaN缓冲层（14），未掺杂的GaN层（16），Si掺杂的n-GaN层（18），SLS层（20 ），形成p型电极（30）和n电极（32）的未掺杂GaN层（22），MQW发光层（24），SLS层（26）和p-GaN层（28） 。 MQW发光层（24）具有其中InGaN阱层和AlGaN势垒层交替的结构。 SLS层（20和26）的Al含量比大于5％且小于24％。 MQW发光层（24）中的阱层的In含量比大于3％且小于20％。 阻挡层的Al含量比大于1％且小于30％。 通过将各层的含有率和膜厚度调整为所需值，波长小于400nm的光发光效率提高。

公开(公告)号：US20060175600A1

公开(公告)日：2006-08-10

申请号：US10516703

申请日：2003-06-04

Applicant: Hisao Sato ,  Tomoya Sugahara ,  Shinji Kitazawa ,  Yoshihiko Muramoto ,  Shiro Sakai

Inventor： Hisao Sato ,  Tomoya Sugahara ,  Shinji Kitazawa ,  Yoshihiko Muramoto ,  Shiro Sakai

IPC: H01L31/109 ,  H01L21/00

CPC classification number: H01L33/32 ,  B82Y20/00 ,  H01L33/04 ,  H01L33/06

Abstract: A light-emitting element using GaN. On a substrate (10), formed are an SiN buffer layer (12), a GaN buffer layer (14), an undoped GaN layer (16), an Si-doped n-GaN layer (18), an SLS layer (20), an undoped GaN layer (22), an MQW light-emitting layer (24), an SLS layer (26), and a p-GaN layer (28), forming a p electrode (30) and an n electrode (32). The MQW light-emitting layer (24) has a structure in which InGaN well layers and AlGaN barrier layers are alternated. The Al content ratios of the SLS layers (20, and 26) are more than 5% and less than 24%. The In content ratio of the well layer in the MQW light-emitting layer (24) is more than 3% and less than 20%. The Al content ratio of the barrier layer is more than 1% and less than 30%. By adjusting the content ratio and film thickness of each layer to a desired value, the light luminous efficiency for wavelength of less than 400 nm is improved.

Abstract translation: 使用GaN的发光元件。 在形成的衬底（10）上形成SiN缓冲层（12），GaN缓冲层（14），未掺杂的GaN层（16），Si掺杂的n-GaN层（18），SLS层（20 ），形成p型电极（30）和n电极（32）的未掺杂GaN层（22），MQW发光层（24），SLS层（26）和p-GaN层（28） 。 MQW发光层（24）具有其中InGaN阱层和AlGaN势垒层交替的结构。 SLS层（20和26）的Al含量比大于5％且小于24％。 MQW发光层（24）中的阱层的In含量比大于3％且小于20％。 阻挡层的Al含量比大于1％且小于30％。 通过将各层的含有率和膜厚度调整为所需值，波长小于400nm的光发光效率提高。

公开(公告)号：US20050236642A1

公开(公告)日：2005-10-27

申请号：US10521544

申请日：2003-07-01

Applicant: Shiro Sakai ,  Tomoya Sugahara

Inventor： Shiro Sakai ,  Tomoya Sugahara

IPC: H01L33/06 ,  H01L33/12 ,  H01L33/32 ,  H01L33/00

CPC classification number: H01L33/32 ,  B82Y20/00 ,  H01L33/06

Abstract: An LED emitting light of wavelength mainly 375 nm or below. The LED includes a GaN layer (16), an n-clad layer (20), an AlInGaN buffer layer (22), a light emitting layer (24), a p-clad layer (26), a p-electrode (30), and an n-electrode (32) arranged on a substrate (10). The light emitting layer (24) has a multi-layer quantum well structure (MQW) in which an InGaN well layer and an AlInGaN barrier layer are superimposed. The quantum well structure increases the effective band gap of the InGaN well layer and reduces the light emitting wavelength. Moreover, by using the AlInGaN buffer layer (22) as the underlying layer of the light emitting layer (24), it is possible to effectively inject electrons into the light emitting layer (24), thereby increasing the light emitting efficiency.

Abstract translation: 发射波长主要为375nm或以下的LED的LED。 LED包括GaN层（16），n覆盖层（20），AlInGaN缓冲层（22），发光层（24），p覆盖层（26），p电极（30） ）和布置在基板（10）上的n电极（32）。 发光层（24）具有叠层InGaN阱层和AlInGaN阻挡层的多层量子阱结构（MQW）。 量子阱结构增加了InGaN阱层的有效带隙并降低了发光波长。 此外，通过使用AlInGaN缓冲层（22）作为发光层（24）的下层，可以有效地将电子注入到发光层（24）中，从而提高发光效率。

公开(公告)号：US06666921B2

公开(公告)日：2003-12-23

申请号：US10079852

申请日：2002-02-22

Applicant: Shiro Sakai ,  Yukichi Takamatsu ,  Yuji Mori ,  Hong Xing Wang ,  Yoshiyasu Ishihama ,  Yutaka Amijima

Inventor： Shiro Sakai ,  Yukichi Takamatsu ,  Yuji Mori ,  Hong Xing Wang ,  Yoshiyasu Ishihama ,  Yutaka Amijima

IPC: C23C1600

CPC classification number: C23C16/45502 ,  C23C16/455 ,  C23C16/45591 ,  C30B25/14

Abstract: The present invention provides a chemical vapor deposition apparatus for a semiconductor film, containing a horizontal tubular reactor, a susceptor, a heater, a feed gas introduction portion and a reaction gas exhaust portion, where part of the tubular reactor walls inclines downward from the upstream side of the feed gas passageway towards the downstream side thereof. The present invention also provides a chemical vapor deposition method using the apparatus.

Abstract translation: 本发明提供了一种用于半导体膜的化学气相沉积装置，其包含水平管状反应器，基座，加热器，进料气体引入部分和反应气体排出部分，其中部分管式反应器壁从上游向下倾斜 进料气体通道的一侧朝向其下游侧。 本发明还提供使用该装置的化学气相沉积方法。

公开(公告)号：US06610606B2

公开(公告)日：2003-08-26

申请号：US10107549

申请日：2002-03-27

Applicant: Shiro Sakai ,  Yves Lacroix

Inventor： Shiro Sakai ,  Yves Lacroix

IPC: H01L21302

CPC classification number: H01L33/007 ,  H01L29/2003 ,  H01L29/452

Abstract: A method for manufacturing a GaN-based semiconductor device in which an ohmic contact can be provided between the semiconductor layer and the electrode material. In a method for manufacturing wherein an n-GaN layer, an emissive layer, a p-GaN layer are formed on a substrate in that order; etching is performed to expose a portion of the n-GaN layer; and a negative electrode is formed on the n-GaN layer, the etching is performed in two sub-steps, an etching step using BCl3 gas and an etching step using Cl2 gas. The surface of the n-GaN layer is exposed in the first sub-step and the B (boron) contamination layer is removed in the second sub-step.

Abstract translation: 一种用于制造其中可以在半导体层和电极材料之间提供欧姆接触的GaN基半导体器件的方法。 在其中在衬底上依次形成n-GaN层，发光层，p-GaN层的制造方法中， 进行蚀刻以暴露n-GaN层的一部分; 并且在n-GaN层上形成负极，在两个子步骤中进行蚀刻，使用BCl 3气体的蚀刻步骤和使用Cl 2气体的蚀刻步骤进行蚀刻。 在第一子步骤中露出n-GaN层的表面，在第二子步骤中去除B（硼）污染层。

公开(公告)号：US06592674B2

公开(公告)日：2003-07-15

申请号：US09962143

申请日：2001-09-26

Applicant: Shiro Sakai ,  Yukichi Takamatsu ,  Yuji Mori ,  Hiroyuki Naoi ,  Hong Xing Wang ,  Yoshiyasu Ishihama ,  Yutaka Amijima

Inventor： Shiro Sakai ,  Yukichi Takamatsu ,  Yuji Mori ,  Hiroyuki Naoi ,  Hong Xing Wang ,  Yoshiyasu Ishihama ,  Yutaka Amijima

IPC: C23C1600

CPC classification number: C23C16/45568 ,  C23C16/455 ,  C30B25/02 ,  C30B25/14 ,  C30B29/406

Abstract: There are disclosed an apparatus and a method for chemical vapor deposition for a semiconductor film and the like, wherein a feed gas is supplied in a horizontal tubular reactor in the direction parallel to a substrate; a forcing gas is supplied therein in the direction perpendicular to the substrate; and the flow rate per unit area of the forcing gas which is supplied from a forcing gas introduction portion into the reactor is made lower in the central portion of the forcing gas introduction portion than in the peripheral portion thereof, or lower in the middle of a feed gas passageway than at both the end portions of the passageway. It is made possible by the apparatus and method to assure high quality crystals without generating a deposit of decomposed products or reaction products on a tubular reactor wall in opposition to the substrate even in the case of carrying out chemical vapor deposition of a large-sized substrate or simultaneously conducting that of a plurality of substrates, or performing the same at a high temperature.

公开(公告)号：US06517885B2

公开(公告)日：2003-02-11

申请号：US09782623

申请日：2001-02-13

Applicant: Makoto Sakai ,  Hisao Tanaka ,  Shiro Sakai

Inventor： Makoto Sakai ,  Hisao Tanaka ,  Shiro Sakai

IPC: A23L101

CPC classification number: A23L27/18

Abstract: A process is provided for the production of a pressed mustard cake from mustard seed, as well as mustard powder yielded from the milling of the mustard cake of the process. Employing strict temperature controls at key points in the process, this process yields a mustard cake and mustard powder of increased pungency, good flavor, enhanced protein content and enhanced preservability by limiting the degradation of key components in the mustard seed by excessive temperatures in the process.

Abstract translation: 提供了用于从芥菜种子生产压榨芥末蛋糕以及从该方法的芥末饼的研磨产生的芥末粉末的方法。 在该过程的关键点采用严格的温度控制，该方法通过在过程中过度温度限制芥子籽中关键组分的降解，产生芥子饼和芥末粉，其具有增加的刺激性，良好的风味，增强的蛋白质含量和增强的保存性 。

公开(公告)号：US5578891A

公开(公告)日：1996-11-26

申请号：US457174

申请日：1995-06-01

Applicant: Shiro Sakai ,  Takehisa Okamoto ,  Makoto Nakamura

Inventor： Shiro Sakai ,  Takehisa Okamoto ,  Makoto Nakamura

IPC: H01J43/20 ,  H01J43/06 ,  H01J43/18

CPC classification number: H01J43/06

Abstract: An electron multiplier according to this invention comprises dynodes DY1 .about.DY16 arranged in multi-stages along a direction of incidence of an energy beam for, upon incidence of the energy beam, gradually multiplying secondary electrons to emit the same, a collection electrode A for receiving electrons emitted from that of the dynodes on a last stage, and resistors R1 .about.R16 inserted between the respective dynodes and their adjacent ones, the dynodes, the collecting electrode, and the resistors being mounted between two support plates 10a, 10b disposed in parallel with each other, the resistors being arranged in two rows which sandwich the dynodes.

Abstract translation: 根据本发明的电子倍增器包括沿着能量束的入射方向多级布置的倍增电极DY1差分DY16，用于在能量束入射时，逐渐地将二次电子发射相同，用于接收的收集电极A 电子发射自最后一级的倍增电极的电子，以及插入相应的倍增电极及其相邻电极之间的电阻器R1差分R16，倍增电极，集电极和电阻器被安装在两个平行于 彼此之间，电阻器被排列成两行，夹着倍增极。

公开(公告)号：US4928154A

公开(公告)日：1990-05-22

申请号：US325115

申请日：1989-03-20

Applicant: Masayoshi Umeno ,  Shiro Sakai ,  Shinichiro Yahagi

Inventor： Masayoshi Umeno ,  Shiro Sakai ,  Shinichiro Yahagi

IPC: H01L21/20 ,  H01L29/04 ,  H01L29/267 ,  H01L31/0693 ,  H01L31/105 ,  H01L31/18 ,  H01L33/00

CPC classification number: H01L31/0693 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02546 ,  H01L21/02573 ,  H01L21/0262 ,  H01L29/045 ,  H01L29/267 ,  H01L31/105 ,  H01L31/184 ,  H01L33/0066 ,  Y02E10/544 ,  Y10S117/902 ,  Y10S148/072 ,  Y10S148/097 ,  Y10S148/16 ,  Y10S438/933 ,  Y10S438/938

Abstract: A semiconductor wafer having an epitaxial GaAs layer, including a monocrystalline Si substrate having a major surface which is inclined at an off angle between 0.5.degree. and 5.degree. with respect to (100); and at least one intermediate layer epitaxially grown on the major surface of the monocrystalline Si substrate, as a buffer layer for accommodating a lattice mismatch between the Si substrate and the epitaxial GaAs layer which is epitaxially grown on a major surface of a top layer of the at least one intermediate layer. The at least one intermediate layer may comprise one or more GaP/GaAsP, GaAsP/GaAs superlattice layers. The wafer may be used to produce a semiconductor light emitting element which has a plurality of crystalline GaAs layers including a light emitting layer epitaxially grown on the GaAs layer on the intermediate layer. The wafer may also be used to produce a compound semiconductor device such as amplifying and switching elements, light emitting and receiving elements and photovolataic elements. Methods for producing the semiconductor wafer, light emitting element and compound semiconductor devices are also disclosed.

Abstract translation: 一种具有外延GaAs层的半导体晶片，包括具有相对于（100）在0.5度和5度之间的偏离角倾斜的主表面的单晶Si衬底; 以及在单晶Si衬底的主表面上外延生长的至少一个中间层，作为用于容纳Si衬底和外延生长在外延GaAs层上的外延GaAs层之间的晶格失配的缓冲层 至少一个中间层。 至少一个中间层可以包括一个或多个GaP / GaAsP，GaAsP / GaAs超晶格层。 该晶片可以用于制造半导体发光元件，该半导体发光元件具有多个晶体GaAs层，包括在中间层上的GaAs层外延生长的发光层。 晶片也可以用于制造诸如放大和开关元件，发光和接收元件和光电元件的化合物半导体器件。 还公开了制造半导体晶片，发光元件和化合物半导体器件的方法。

公开(公告)号：US4789421A

公开(公告)日：1988-12-06

申请号：US780910

申请日：1985-09-27

Applicant: Masayoshi Umeno ,  Shiro Sakai ,  Tetsuo Soga

Inventor： Masayoshi Umeno ,  Shiro Sakai ,  Tetsuo Soga

IPC: C30B29/40 ,  C30B29/42 ,  H01L21/18 ,  H01L21/205 ,  H01L29/267

CPC classification number: H01L29/267 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02546 ,  H01L21/0262 ,  Y10S148/149

Abstract: A GaAs growth crystal comprises a Si substrate, an intermediate layer formed on the substrate and a GaAs layer grown on the intermediate layer. The intermediate layer includes constituent GaP/GaAsP and GaAsP/GaAs superlattice layers and additionally AlP and AlGaP thin films.

Abstract translation: GaAs生长晶体包括Si衬底，形成在衬底上的中间层和在中间层上生长的GaAs层。 中间层包括GaP / GaAsP和GaAsP / GaAs超晶格层以及另外的AlP和AlGaP薄膜。