公开(公告)号：US20250111987A1

公开(公告)日：2025-04-03

申请号：US18978920

申请日：2024-12-12

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01F27/32 ,  H01F27/02 ,  H01F27/28 ,  H01F41/04 ,  H01L23/495 ,  H01L23/522 ,  H01L23/58 ,  H01L25/00 ,  H01L25/18

Abstract: A magnetic assembly includes a multilevel lamination or metallization structure with a core dielectric layer, dielectric stack layers, a high permittivity dielectric layer, and first and second patterned conductive features, the dielectric stack layers having a first relative permittivity, the high permittivity dielectric layer extends between and contacting the first patterned conductive feature and one of the dielectric stack layers or the core dielectric layer, the high permittivity dielectric layer has a second relative permittivity, and the second relative permittivity is at least 1.5 times the first relative permittivity to mitigate dielectric breakdown in isolation products.

公开(公告)号：US20250105104A1

公开(公告)日：2025-03-27

申请号：US18475563

申请日：2023-09-27

Applicant: Texas Instruments Incorporated

Inventor： Li Jiang ,  Rey Javier ,  Guangxu Li ,  Enis Tuncer

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: An electronic device includes a package structure having four lateral corners, a semiconductor die at least partially enclosed inside the package structure and attached to a die attach pad, conductive leads at least partially exposed outside the package structure along the four lateral sides, a first one of the conductive leads electrically connected to the semiconductor die, an instance of a first conductive feature partially exposed outside the package structure at each of the corners, and an instance of a second conductive feature partially exposed outside the package structure and contacting a respective instance of the first conductive feature at each of the corners, the instance of the second conductive feature exposed outside the package structure along the first side.

公开(公告)号：US11838004B2

公开(公告)日：2023-12-05

申请号：US16356890

申请日：2019-03-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Enis Tuncer ,  Abram Castro

IPC: H03H9/10

CPC classification number: H03H9/1042 ,  H03H9/1007

Abstract: An assembly including an electrical connection substrate formed of material having a Young's modulus of less than about 10 MPa, an acoustic device die having opposite end portions mounted on and electrically connected to the electrical connection substrate and a mold compound layer encapsulating the acoustic device die and interfacing with the substrate.

公开(公告)号：US20230298979A1

公开(公告)日：2023-09-21

申请号：US18322369

申请日：2023-05-23

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/34 ,  H01L23/00

CPC classification number: H01L23/49568 ,  H01L21/4821 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/34 ,  H01L23/49513 ,  H01L23/49558 ,  H01L23/49586 ,  H01L24/48 ,  H01L24/83 ,  H01L24/45 ,  H01L2224/48175

Abstract: In a described example, an apparatus includes: a package substrate having a die pad configured for mounting a semiconductor die, a first lead connected to the die pad, and a second lead spaced from and electrically isolated from the die pad; a spacer dielectric mounted on the die pad; a semiconductor die including a temperature sensor mounted on the spacer dielectric; electrical connections coupling the semiconductor die to the second lead; and mold compound covering the semiconductor die, the die pad, the electrical connections, and a portion of the package substrate, with portions of the first lead and portions of the second lead exposed from the mold compound to form terminals for a packaged temperature sensor device.

公开(公告)号：US11756882B2

公开(公告)日：2023-09-12

申请号：US17138906

申请日：2020-12-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Enis Tuncer ,  Alejandro Hernandez-Luna

IPC: H01L23/525 ,  H01L23/528 ,  H01L23/31 ,  H01L23/495 ,  H01L23/48

CPC classification number: H01L23/5256 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/4952 ,  H01L23/49575 ,  H01L23/5283

Abstract: A semiconductor package includes a metallic pad and leads, a semiconductor die including a semiconductor substrate attached to the metallic pad, and a conductor including a sacrificial fuse element above the semiconductor substrate, the sacrificial fuse element being electrically coupled between one of the leads and at least one terminal of the semiconductor die, and a multilayer dielectric between the sacrificial fuse element and the semiconductor substrate, the multilayer dielectric forming one or more planar gaps beneath a profile of the sacrificial fuse element.

公开(公告)号：US20230187348A1

公开(公告)日：2023-06-15

申请号：US17546383

申请日：2021-12-09

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01L23/525 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/5256 ,  H01L24/48 ,  H01L23/3107 ,  H01L21/56 ,  H01L24/49 ,  H01L24/43 ,  H01L2224/48175 ,  H01L2224/49421 ,  H01L2224/49427 ,  H01L2224/4321

Abstract: An electronic device has a fuse circuit including a semiconductor die and first and second bond wires, the semiconductor die having a bond pad and a fuse, the fuse having first and second portions, the bond pad coupled to the first portion of the fuse, and the second portion of the fuse coupled to a protected circuit, the first bond wire having a first end coupled to the bond pad and a second end coupled to a conductive terminal, and the second bond wire having a first end coupled to the second end of the first bond wire and a second end coupled to the conductive terminal.

公开(公告)号：US20230094556A1

公开(公告)日：2023-03-30

申请号：US17491451

申请日：2021-09-30

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01L49/02 ,  H01L23/64 ,  H01L25/065 ,  H01L23/00

Abstract: In a described example, an apparatus includes a transformer including: an isolation dielectric layer with a first surface and a second surface opposite the first surface; a first inductor formed over the first surface, the first inductor comprising a first layer of ferrite material, and a first coil at least partially covered by the first layer of ferrite material; and a second inductor formed over the second surface, the second inductor comprising a second layer of ferrite material and a second coil at least partially covered by the second layer of ferrite material.

公开(公告)号：US11614482B1

公开(公告)日：2023-03-28

申请号：US17566607

申请日：2021-12-30

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: G01R31/28 ,  G01R15/20

Abstract: A method includes placing a semiconductor device package in a test handler, the semiconductor device package having leads of a first portion of a package substrate extending from a mold compound and leads of a second portion isolated from the first portion extending from the mold compound; contacting the first portion with a first and a second conductive slug; contacting the second portion with a third and a fourth conductive slug; contacting a first surface of the mold compound with a first plunger having a conductive plate and an insulating tip; contacting an opposite second surface of the mold compound with a second plunger having a conductive plate and an insulating tip; and placing a high voltage on the first conductive slug while placing approximately half the high voltage on the conductive plate of the first plunger, and placing a ground voltage on the third conductive slug.

公开(公告)号：US11598742B2

公开(公告)日：2023-03-07

申请号：US17137251

申请日：2020-12-29

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer ,  Vikas Gupta

IPC: H01L21/768 ,  G01N27/22 ,  H01L23/522 ,  H01L23/00

Abstract: Described examples include a sensor device having at least one conductive elongated first pillar positioned on a central pad of a first conductor layer over a semiconductor substrate, the first pillar extending in a first direction normal to a plane of a surface of the first conductor layer. Conductive elongated second pillars are positioned in normal orientation on a second conductor layer over the semiconductor substrate, the conductive elongated second pillars at locations coincident to via openings in the first conductor layer. The second conductor layer is parallel to and spaced from the first conductor layer by at least an insulator layer, the conductive elongated second pillars extending in the first direction through a respective one of the via openings. The at least one conductive elongated first pillar is spaced from surrounding conductive elongated second pillars by gaps.

公开(公告)号：US20220319988A1

公开(公告)日：2022-10-06

申请号：US17218941

申请日：2021-03-31

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01L23/525 ,  H01L23/498 ,  H01L23/00

Abstract: In a described example, an apparatus includes: a package substrate having a die pad configured for mounting a semiconductor die, and leads spaced from the die pad; a semiconductor die mounted on the die pad; a fuse mounted to a lead, the fuse having a fuse element coupled between a fuse cap and the lead, the fuse having a fuse body with an opening surrounding the fuse element, the fuse cap attached to the fuse body; electrical connections coupling the semiconductor die to the fuse; and mold compound covering the semiconductor die, the fuse, the electrical connections, and a portion of the package substrate, with portions of the leads exposed from the mold compound to form terminals.