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公开(公告)号：US12160259B2
公开(公告)日：2024-12-03
申请号：US17544795
申请日：2021-12-07
Applicant: Texas Instruments Incorporated
Inventor： Sundarrajan Rangachari , Nagalinga Swamy Basayya Aremallapur , Kalyan Gudipati , Divyeshkumar Mahendrabhai Patel , Venkateshwara Reddy Pothapu , Aravind Vijayakumar , Sarma Sundareswara Gunturi , Jaiganesh Balakrishnan
Abstract: A technique for reinitializing a coupled circuit, the technique including receiving a common configuration value associated with states of a coupled circuit, tracking states associated with the coupled circuit while the coupled circuit is in a low power state based on the common configuration value, receiving the tracked state associated with the coupled circuit, receiving a scaling value associated with the coupled circuit, determining a current state of the coupled circuit based on the tracked state and the scaling value, and transmitting an indication of the current state to the coupled circuit when the coupled circuit has exited the low power state.
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公开(公告)号：US20230336200A1
公开(公告)日：2023-10-19
申请号：US18318800
申请日：2023-05-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jaiganesh Balakrishnan
IPC: H04B1/12 , H04B1/16 , H04H40/72 , H04B17/318 , H04B17/20 , H04B17/336 , H04B1/10
CPC classification number: H04B1/12 , H04B1/1646 , H04H40/72 , H04B17/318 , H04B17/20 , H04B17/336 , H04B1/10 , H04B1/1027 , H04B2001/1054
Abstract: A wireless receiver includes a down converter module operable to deliver a signal having a signal bandwidth that changes over time, a dynamically controllable filter module having a filter bandwidth and fed by said down converter module, and a measurement module operable to at least approximately measure the signal bandwidth, said dynamically controllable filter module responsive to said measurement module to dynamically adjust the filter bandwidth to more nearly match the signal bandwidth as it changes over time, whereby output from said filter module is noise-reduced. Other wireless receivers, electronic circuits, and processes for their operation are disclosed.
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公开(公告)号：US20230275594A1
公开(公告)日：2023-08-31
申请号：US17682753
申请日：2022-02-28
Applicant: Texas Instruments Incorporated
Inventor： Pankaj Gupta , Ajai Paulose , Sreenath Narayanan Potty , Divyansh Jain , Jaiganesh Balakrishnan , Jawaharlal Tangudu , Aswath VS , Girish Nadiger , Ankur Jain
IPC: H03M1/06
CPC classification number: H03M1/0617
Abstract: An example apparatus includes: nonlinearity function selection circuitry with an output, the nonlinearity function selection circuitry to select a type of a nonlinearity function, the nonlinearity function to model nonlinearity portions of data output from an analog-to-digital converter, nonlinearity function term generation circuitry with a first input coupled to the output, the nonlinearity function term generation circuitry to generate one or more nonlinearity function terms of the nonlinearity function based on the type of the nonlinearity function and the data, and coefficient determination circuitry with a second input coupled to the output, the coefficient determination circuitry to determine one or more nonlinearity function coefficients based on the one or more nonlinearity function terms, the nonlinearity portions of the data to be compensated based on the one or more nonlinearity function coefficients.
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公开(公告)号：US11736138B2
公开(公告)日：2023-08-22
申请号：US17493943
申请日：2021-10-05
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriram Murali , Jaiganesh Balakrishnan , Pooja Sundar , Harshavardhan Adepu , Wenjing Lu , Yeswanth Guntupalli
CPC classification number: H04B1/40 , H04B1/0075
Abstract: A digital up-converter (DUC) includes conjugate-mixer-combiner. The conjugate-mixer-combiner includes a pre-combiner configured to generate combinations of a first in-phase (I) value to be transmitted at a first frequency of a first frequency band, a first quadrature (Q) value to be transmitted at the first frequency of a first frequency band, a second I value for to be transmitted at a second frequency of a second frequency band, and a second Q value to be transmitted at the second frequency of a second frequency band. The conjugate-mixer-combiner further includes a plurality of multipliers collectively configured to shift the combinations based on an average difference between the first frequency and the second frequency.
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公开(公告)号：US11695602B2
公开(公告)日：2023-07-04
申请号：US17538460
申请日：2021-11-30
Applicant: Texas Instruments Incorporated
IPC: H04L27/14
CPC classification number: H04L27/14
Abstract: A digital down converter (DDC) that improves efficiency by taking advantage of the periodicity of the coarse mixing process and the memory inherent in the convolution operation performed by decimation filters. In embodiments, the DDC filters and decimates a received signal to generate subfilter outputs and coarse mixes the subfilter outputs for each frequency band of interest. Accordingly, the DDC eliminates the need for separate decimation filters for each of the in-phase (I-phase) and quadrature (Q-phase) signals of each frequency band. In some embodiments, for each frequency band, the DDC combines the subfilter outputs into partial sums for each of the I- and Q-phases. In some of those embodiments, the coarse mixing operation is performed by multiplying the partial sums by real multiplicands and performing a simple post-rotation operation. In those embodiments, the DDC significantly reduces the number of multiplication operations required to perform the coarse mixing process.
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Patent Agency Ranking
公开(公告)号：US11489517B2
公开(公告)日：2022-11-01
申请号：US17558794
申请日：2021-12-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriram Murali , Jaiganesh Balakrishnan , Ram Narayan Krishna Nama Mony , Pooja Sundar
Abstract: A circuit includes a noise generator and a delay element. The output of the noise generator couples to the input of the delay element. The output of the delay element is coupled to a first input of a logic circuit, and the output of the noise generator is coupled to a second input of the logic circuit. The output of the logic circuit is coupled to a first control input of a waveform storage circuit. The waveform storage circuit is configured to produce a first digital waveform on its output responsive to a first logic state on the output of the logic circuit and to produce a second digital waveform on its output responsive to a second logic state on the output of the logic circuit. A sequencer has a sequencer output coupled to the second control input of the waveform storage circuit.
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公开(公告)号：US11356125B2
公开(公告)日：2022-06-07
申请号：US16953947
申请日：2020-11-20
Applicant: Texas Instruments Incorporated
Inventor： Jawaharlal Tangudu , Yeswanth Guntupalli , Kalyan Gudipati , Robert Clair Keller , Wenjing Lu , Jaiganesh Balakrishnan , Harsh Garg , Bragadeesh S , Raju Kharataram Chaudhari , Francesco Dantoni
Abstract: An integrated circuit comprises an input, a digital step attenuator, an analog-to-digital converter, a first output, a second output, a first bandwidth filter, a first band attack detector, a first band decay detector, a second bandwidth filter, a second band attack detector, a second band decay detector, and an automatic gain control. The ADC is configured to output a digital signal including a first and a second frequency range. The first and second bandwidth filters are configured to extract respective digital signals comprising the first and second frequency ranges. The band attack and decay detectors are configured to detect band peaks or decays thereof such that the DSA and External AMP may be controlled by means of the AGC based on the detected band peaks or decays, and ADC attack and ADC decay.
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公开(公告)号：US11211959B2
公开(公告)日：2021-12-28
申请号：US16838685
申请日：2020-04-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jaiganesh Balakrishnan
IPC: H04B1/12 , H04B1/16 , H04B1/10 , H04H40/72 , H04B17/318 , H04B17/20 , H04B17/336
Abstract: A wireless receiver (10) includes a down converter module (210) operable to deliver a signal having a signal bandwidth that changes over time, a dynamically controllable filter module (200) having a filter bandwidth and fed by said down converter module (210), and a measurement module (295) operable to at least approximately measure the signal bandwidth, said dynamically controllable filter module (200) responsive to said measurement module (295) to dynamically adjust the filter bandwidth to more nearly match the signal bandwidth as it changes over time, whereby output from said filter module (200) is noise-reduced. Other wireless receivers, electronic circuits, and processes for their operation are disclosed.
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公开(公告)号：US20210159924A1
公开(公告)日：2021-05-27
申请号：US16953947
申请日：2020-11-20
Applicant: Texas Instruments Incorporated
Inventor： Jawaharlal Tangudu , Yeswanth Guntupalli , Kalyan Gudipati , Robert Clair Keller , Wenjing Lu , Jaiganesh Balakrishnan , Harsh Garg , Bragadeesh S , Raju Kharataram Chaudhari , Francesco Dantoni
Abstract: An integrated circuit comprises an input, a digital step attenuator, an analog-to-digital converter, a first output, a second output, a first bandwidth filter, a first band attack detector, a first band decay detector, a second bandwidth filter, a second band attack detector, a second band decay detector, and an automatic gain control. The ADC is configured to output a digital signal including a first and a second frequency range. The first and second bandwidth filters are configured to extract respective digital signals comprising the first and second frequency ranges. The band attack and decay detectors are configured to detect band peaks or decays thereof such that the DSA and External AMP may be controlled by means of the AGC based on the detected band peaks or decays, and ADC attack and ADC decay.
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公开(公告)号：US10979262B2
公开(公告)日：2021-04-13
申请号：US16902529
申请日：2020-06-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: IQ mismatch correction for analog chain IQ mismatch impairments is based on a two-filter architecture. In either RX or TX, an IQmc mismatch corrector (digital chain) filters I and Q digital signals, and includes an I-path to receive the I signal, and a Q-path to receive the Q signal, and is configured with two filters: an in-path filter to filter either the I signal or the Q signal received in the same path; and a cross-path filter to filter either the I signal or the Q signal received in the other path. The IQmc mismatch corrector can include: an I-path delay element to provide a delay to the I signal corresponding to a delay through either the in-path filter or the cross-path filter; and a Q-path delay element to provide a delay to the Q signal corresponding to a delay through either the in-path filter or the cross-path filter.
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