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    Hierarchical data organization for dense optical flow processing in a computer vision system
    51.
    发明授权
    Hierarchical data organization for dense optical flow processing in a computer vision system 有权

    公开(公告)号：US10824877B2

    公开(公告)日：2020-11-03

    申请号：US15638142

    申请日：2017-06-29

    Applicant: Texas Instruments Incorporated

    Inventor： Hetul Sanghvi ,  Mihir Narendra Mody ,  Niraj Nandan ,  Anish Reghunath ,  Michael Peter Lachmayr

    IPC: G06K9/00 ,  G06T7/20 ,  G06T1/00 ,  G06T7/269

    Abstract: A computer vision system is provided that includes an image generation device configured to capture consecutive two dimensional (2D) images of a scene, a first memory configured to store the consecutive 2D images, a second memory configured to store a growing window of consecutive rows of a reference image and a growing window of consecutive rows of a current image, wherein the reference image and the current image are a pair of consecutive 2D images stored in the first memory, a third memory configured to store a sliding window of pixels fetched from the growing window of the reference image, wherein the pixels in the sliding window are stored in tiles, and a dense optical flow engine (DOFE) configured to determine a dense optical flow map for the pair of consecutive 2D images, wherein the DOFE uses the sliding window as a search window for pixel correspondence searches.

    Bandwidth controlled data synchronization for image and vision processor
    52.
    发明授权
    Bandwidth controlled data synchronization for image and vision processor 有权

    公开(公告)号：US10776167B2

    公开(公告)日：2020-09-15

    申请号：US15269952

    申请日：2016-09-19

    Applicant: Texas Instruments Incorporated

    Inventor： Niraj Nandan ,  Hetul Sanghvi ,  Mihir Narendra Mody

    IPC: G06F9/46 ,  G06F9/50 ,  G06F9/48 ,  G06F11/07 ,  G06F9/52

    Abstract: A hardware thread scheduler (HTS) is provided for a multiprocessor system. The HTS is configured to schedule processing of multiple threads of execution by resolving data dependencies between producer modules and consumer modules for each thread. Pattern adaptors may be provided in the scheduler that allows mixing of multiple data patterns across blocks of data. Transaction aggregators may be provided that allow re-using the same image data by multiple threads of execution while the image date remains in a given data buffer. Bandwidth control may be provided using programmable delays on initiation of thread execution. Failure and hang detection may be provided using multiple watchdog timers.

    THREAD SCHEDULING FOR MULTITHREADED DATA PROCESSING ENVIRONMENTS
    53.
    发明申请
    THREAD SCHEDULING FOR MULTITHREADED DATA PROCESSING ENVIRONMENTS 审中-公开

    公开(公告)号：US20190286483A1

    公开(公告)日：2019-09-19

    申请号：US16298709

    申请日：2019-03-11

    Applicant: Texas Instruments Incorporated

    Inventor： Kedar Chitnis ,  Mihir Narendra Mody ,  Jesse Gregory Villarreal, JR. ,  Lucas Carl Weaver ,  Brijesh Jadav ,  Niraj Nandan

    IPC: G06F9/48 ,  G06F9/54

    Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. Example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. Disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled.

    ADAPTIVE BILATERAL (BL) FILTERING FOR COMPUTER VISION
    55.
    发明申请
    ADAPTIVE BILATERAL (BL) FILTERING FOR COMPUTER VISION 审中-公开

    公开(公告)号：US20190130534A1

    公开(公告)日：2019-05-02

    申请号：US16178200

    申请日：2018-11-01

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mihir Narendra Mody ,  Shashank Dabral ,  Jesse Gregory Villarreal ,  William Wallace ,  Niraj Nandan

    IPC: G06T5/00 ,  G06K9/46 ,  G06T5/20

    Abstract: A method for filtering noise for imaging includes receiving an image frame having position and range data. A filter size divides the frame into filter windows for processing each of the filter windows. For the first pixel, a space to the center pixel and a range difference between this pixel and the center pixel is determined and used for choosing a selected weight from weights in a 2D weight LUT including weighting for space and range difference, a filtered range value is calculated by applying the selected 2D weight to the pixel, and the range, filtered range value and selected 2D weight are summed. The determining, choosing, calculating and summing are repeated for at least the second pixel. A total sum of contributions from the first and second pixel are divided by the sum of selected 2D weights to generate a final filtered range value for the center pixel.

    High Perfomance DMA Controller for Video Processors
    57.
    发明申请
    High Perfomance DMA Controller for Video Processors 有权
    用于视频处理器的高性能DMA控制器

    公开(公告)号：US20150016499A1

    公开(公告)日：2015-01-15

    申请号：US14330553

    申请日：2014-07-14

    Applicant: Texas Instruments Incorporated

    Inventor： Niraj Nandan

    IPC: H04N19/433 ,  G06F13/28

    CPC classification number: G06F13/28

    Abstract: This invention for a VDMA will enable ultra HD resolution (4K) encode/decode at 30 frames per second. This invention maximizes interconnect/DDR utilization and reduces CPU intervention using virtual alignment, sub-tile optimization, transaction breakdown strategy, 4D indexing, a dedicated interface with the host and frame padding. The VDMA has separate buffers for non-determinative synchronous data transfers and determinative asynchronous data transfers.

    Abstract translation: 用于VDMA的本发明将实现每秒30帧的超高分辨率（4K）编码/解码。 本发明使互连/ DDR利用率最大化，并使用虚拟对准，子块优化，事务分解策略，4D索引，与主机和帧填充的专用接口来减少CPU干预。 VDMA具有用于非确定性同步数据传输和确定性异步数据传输的单独缓冲器。

    Sample Adaptive Offset (SAO) Filtering in Video Coding
    58.
    发明申请
    Sample Adaptive Offset (SAO) Filtering in Video Coding 有权
    视频编码中的自适应偏移（SAO）滤波

    公开(公告)号：US20140341287A1

    公开(公告)日：2014-11-20

    申请号：US14279318

    申请日：2014-05-16

    Applicant: Texas Instruments Incorporated

    Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hideo Tamama

    IPC: H04N19/61 ,  H04N19/80

    CPC classification number: H04N19/436 ,  H04N19/117 ,  H04N19/14 ,  H04N19/176 ,  H04N19/182 ,  H04N19/186 ,  H04N19/423 ,  H04N19/82

    Abstract: A method for sample adaptive offset (SAO) filtering of largest coding units (LCUs) of a video frame in an SAO component is provided that includes receiving, by the SAO component, an indication that deblocked pixel blocks of an LCU are available, and applying SAO filtering, by the SAO component, to each pixel block of pixel blocks of an SAO processing area corresponding to the LCU responsive to the indication, wherein pixels of each pixel block of the SAO processing area are filtered in parallel.

    Abstract translation: 提供了一种用于在SAO组件中的视频帧的最大编码单元（LCU）的采样自适应偏移（SAO）滤波的方法，其包括由SAO组件接收到LCU的解块像素块可用的指示，以及应用 通过SAO分量对SAO处理区域的对应于该LCU的SAO处理区域的每个像素块进行SAO滤波，其中SAO处理区域的每个像素块的像素被并行地滤波。

    Optimized edge order for de-blocking filter
    59.
    发明授权
    Optimized edge order for de-blocking filter 有权

    公开(公告)号：US12262061B2

    公开(公告)日：2025-03-25

    申请号：US18219788

    申请日：2023-07-10

    Applicant: Texas Instruments Incorporated

    Inventor： Niraj Nandan ,  Mullangi Venkata Ratna Reddy

    IPC: H04N19/80 ,  H04N19/423 ,  H04N19/86

    Abstract: A de-blocking filter includes a reconstructed memory that is configured to store reconstructed pixels corresponding to a current macroblock of a video image to be filtered. The current macroblock includes a set of sub-blocks, each sub-block having horizontal edges and vertical edges. An internal pixel buffer in the de-blocking filter is configured to store pixels corresponding to the set of sub-blocks from the reconstructed memory, and to store partially filtered pixels corresponding to a set of partially filtered macroblocks. An edge order controller in the de-blocking filter is configured to load the pixels corresponding to the set of sub-blocks into a filter engine from the internal pixel buffer, to filter the set of sub-blocks, such that, at least one horizontal edge is filtered before filtering all vertical edges of the set of sub-blocks.

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