公开(公告)号：EP2741321A3

公开(公告)日：2016-01-20

申请号：EP13195782.1

申请日：2013-12-05

Applicant: J-Devices Corporation

Inventor： Tomonaga, Yoshiyuki ,  Ooida, Mitsuru ,  Watanabe, Katsumi ,  Sato, Hidenari

IPC: H01L23/31 ,  H01L23/433 ,  H01L21/56 ,  H01L23/49

CPC classification number: H01L23/49568 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/4334 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor device having a substrate including a plurality of external terminals on a rear surface and a plurality of bonding terminals electrically connected to the plurality of external terminals on a front surface, a semiconductor chip mounted on the front surface of the substrate, a surface of the chip including a plurality of bonding pads, a plurality of bonding wires connecting between the plurality of bonding pads or between the plurality of bonding terminals and the plurality of bonding wires respectively, a first sealing layer sealing the front surface of the substrate, the plurality of bonding wires and the semiconductor chip, and a second sealing layer comprised of the same material as the first sealing, the second sealing layer being formed above the first sealing layer.

Abstract translation: 一种半导体器件，具有在后表面上具有多个外部端子的基板和与表面上的多个外部端子电连接的多个接合端子，安装在基板的前表面上的半导体芯片， 所述芯片包括多个接合焊盘，多个接合线，分别连接在所述多个接合焊盘之间或者在所述多个接合端子和所述多个接合线之间，密封所述衬底的前表面的第一密封层， 的接合线和半导体芯片，以及由与第一密封相同的材料构成的第二密封层，第二密封层形成在第一密封层的上方。

公开(公告)号：EP2903021A1

公开(公告)日：2015-08-05

申请号：EP14153041.0

申请日：2014-01-29

Applicant: J-Devices Corporation

Inventor： Inoue, Hiroshi ,  Katsumata, Akio ,  Sawachi, Shigenori ,  Yamagata, Osamu

IPC: H01L23/00 ,  H01L25/10

CPC classification number: H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor device (100), having an insulating substrate (102); a semiconductor element (101) which is mounted on one main surface of the insulating substrate via adhesive (103), with an element circuit surface of the semiconductor element facing upwards; a first insulating material layer (104a) which seals the element circuit surface of the semiconductor element and the insulating substrate peripheral thereto; a first metal thin film wire layer (105) which is provided on the first insulating material layer (104a) and a portion of which is exposed to an external surface; a first insulating material layer (104b) which is provided on the first metal thin film wire layer (105); a second insulating material layer (107) which is provided on a main surface of the insulating substrate (102) where the semiconductor element is not mounted; a second metal thin film wire layer (106) which is provided inside the second insulating material layer and a portion of which is exposed to an external surface; a via (108) which passes through the insulating substrate and which electrically connects the first metal thin film wire layer (105) in the first insulating material layer (104a) and the second metal thin film wire layer (106); and an external electrode (109) which is formed on the first metal thin film wire layer (105), the semiconductor device having a structure in which the second metal thin film wire layer, an electrode arranged on the element circuit surface of the semiconductor element, the first metal thin film wire layer, the via and the external electrode formed on the first metal thin film wire layer are electrically connected.

Abstract translation: 一种半导体装置（100），具有对绝缘衬底（102）; 其经由粘合剂（103）安装在所述绝缘基片的一个主表面，与面向上的半导体元件的元件电路表面上的半导体元件（101）的所有; 密封该半导体元件的元件电路表面和外周在其上的绝缘基板的第一绝缘材料层（104A）; 其上设置有第一绝缘材料层（104A）和所有的暴露于外部表面上的一部分上的第1金属薄膜层金属线（105）的所有; 其设置在所述第一金属薄膜层金属线（105）的第一绝缘材料层（104B）; 其设置在其中的半导体元件没有被安装在绝缘基板（102）的主表面上的第二绝缘材料层（107）的所有; 该第二绝缘材料层和所有的暴露于外部表面上的部分的内侧设置的第二金属薄膜层金属线（106）的所有; 通孔（108），通过绝缘基板和通过其电连接在所述第一绝缘材料层中的第一金属薄膜层金属线（105）（104A）和所述第二金属薄膜层金属线（106）; 和所有其在第1金属薄膜布线层（105）上形成了外部电极（109），具有在上电极上的第2金属薄膜布线层的半导体元件的元件电路表面上排列的结构的半导体器件 中，第一金属薄膜层金属线，通孔和形成在所述第1金属薄膜层导线与外部电极电连接。

公开(公告)号：EP2752873A3

公开(公告)日：2014-09-24

申请号：EP14162557.4

申请日：2013-02-28

Applicant: J-Devices Corporation

Inventor： Umeki, Akihiro ,  Hiruta, Yoichi

IPC: H01L25/03 ,  H01L25/065 ,  H01L21/66

CPC classification number: H01L23/28 ,  H01L21/56 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/34 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32155 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor module, having a semiconductor package, which is obtained by mounting and resin-sealing a semiconductor bare chip on a first package substrate; a semiconductor bare chip; and a second package substrate; wherein the semiconductor package is mounted on the second package substrate and the semiconductor bare chip is mounted on the semiconductor package, wherein the semiconductor package is bonded to the second package substrate at the resin surface and electrically connected to the second package substrate by wire bonding.

公开(公告)号：EP2645417A1

公开(公告)日：2013-10-02

申请号：EP13157205.9

申请日：2013-02-28

Applicant: J-Devices Corporation

Inventor： Umeki, Akihiro ,  Hiruta, Yoichi

IPC: H01L25/03 ,  H01L25/065

CPC classification number: H01L23/28 ,  H01L21/56 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/34 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32155 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In the semiconductor module comprising a package substrate, a first semiconductor package, and a semiconductor bare chip, such problems as the occurrence of a wire short caused by warpage of the first semiconductor package and non-filling and the like at the time of resin sealing can be solved.
A semiconductor module (10), having: a semiconductor package (6), which is obtained by mounting and resin-sealing a semiconductor bare chip (1) on a first package substrate (4); a semiconductor bare chip 2; and a second package substrate (12), the semiconductor module being characterized in that the semiconductor package (6) is mounted on the second package substrate (12) and the semiconductor bare chip (2) is mounted on the semiconductor package (6).

Abstract translation: 在包括封装基板，第一半导体封装和半导体裸芯片的半导体模块中，在树脂密封时出现由第一半导体封装的翘曲引起的引线短路等的问题 可以解决 一种半导体模块（10），具有：半导体封装（6），其通过将半导体裸芯片（1）安装并树脂密封在第一封装基板（4）上而获得; 半导体裸芯片2; 和第二封装基板（12），所述半导体模块的特征在于，所述半导体封装（6）安装在所述第二封装基板（12）上，所述半导体裸芯片（2）安装在所述半导体封装（6）上。

公开(公告)号：EP2741321A2

公开(公告)日：2014-06-11

申请号：EP13195782.1

申请日：2013-12-05

Applicant: J-Devices Corporation

Inventor： Tomonaga, Yoshiyuki ,  Ooida, Mitsuru ,  Watanabe, Katsumi ,  Sato, Hidenari

IPC: H01L23/31 ,  H01L23/433 ,  H01L21/56

CPC classification number: H01L23/49568 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/4334 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor device having a substrate including a plurality of external terminals on a rear surface and a plurality of bonding terminals electrically connected to the plurality of external terminals on a front surface, a semiconductor chip mounted on the front surface of the substrate, a surface of the chip including a plurality of bonding pads, a plurality of bonding wires connecting between the plurality of bonding pads or between the plurality of bonding terminals and the plurality of bonding wires respectively, a first sealing layer sealing the front surface of the substrate, the plurality of bonding wires and the semiconductor chip, and a second sealing layer comprised of the same material as the first sealing, the second sealing layer being formed above the first sealing layer.

Abstract translation: 一种半导体装置，其具有：基板，其在背面具有多个外部端子，且在正面具有与所述多个外部端子电连接的多个接合端子;半导体芯片，其搭载于所述基板的表面; 所述芯片包括多个键合焊盘;多个键合线，分别连接所述多个键合焊盘之间或所述多个键合端子与所述多个键合线之间;第一密封层，密封所述衬底的所述前表面，所述多个 以及由与第一密封件相同的材料构成的第二密封层，第二密封层形成在第一密封层上方。

公开(公告)号：EP2720267A1

公开(公告)日：2014-04-16

申请号：EP13188322.5

申请日：2013-10-11

Applicant: J-Devices Corporation

Inventor： Itakura, Satoru ,  Katsumata, Akio ,  Umeki, Akihiro ,  Shiraishi, Yasushi ,  Abe, Junichiro

IPC: H01L25/10 ,  H01L25/065 ,  H01L25/18 ,  G06F3/00

CPC classification number: G11C16/30 ,  G06F3/00 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C7/10 ,  G11C7/1069 ,  G11C11/4096 ,  H01L22/10 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/19105

Abstract: A semiconductor storage device (100) includes a controller package (110) having a BGA terminal on a bottom surface thereof; and one or a plurality of memory packages (120) each including a plurality of semiconductor storage elements and mounted on the controller package. The controller package includes a bottom substrate having the BGA terminal on a bottom surface thereof; a power supply IC, mounted on the bottom substrate, for supplying a plurality of power supplies; and a controller mounted on the bottom substrate and operable by the plurality of power supplies supplied from the power supply IC. The controller provides an interface with an external system via the BGA terminal and controls a read operation from the semiconductor storage elements and a write operation to the semiconductor storage elements.

Abstract translation: 半导体存储装置（100）包括在其底面上具有BGA端子的控制器封装（110） 以及一个或多个存储器封装（120），每个存储器封装（120）包括多个半导体存储元件并且安装在所述控制器封装上。 所述控制器封装包括在其底表面上具有所述BGA端子的底部基板; 电源IC，安装在底部基板上，用于供给多个电源; 以及控制器，其安装在所述底部基板上并且可由所述电源IC提供的所述多个电源操作。 控制器通过BGA终端提供与外部系统的接口，并控制来自半导体存储元件的读取操作和对半导体存储元件的写入操作。

公开(公告)号：EP2634796A3

公开(公告)日：2015-03-25

申请号：EP12189403.4

申请日：2012-10-22

Applicant: J-Devices Corporation

Inventor： Sawachi, Shigenori ,  Yamagata, Osamu ,  Inoue, Hiroshi ,  Itakura, Satoru ,  Chikai, Tomoshige ,  Hori, Masahiko ,  Katsumata, Akio

IPC: H01L23/538 ,  H01L21/98

Abstract: A semiconductor device, comprising: a semiconductor element; a support substrate (1); an insulating material layer (4) for sealing the semiconductor element (2a, 2b) and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer (4), with a part thereof being exposed on an external surface; and metal vias (9) provided in the insulating material layer (4) and electrically connected to the metal thin film wiring layer, wherein the semiconductor element (2a, 2b) is provided in a plurality, and the respective semiconductor elements (2a, 2b) are stacked via an insulating material (4) such that a circuit surface of each semiconductor element (2a, 2b) faces the metal thin film wiring layer, and electrode pads of each semiconductor element (2a) are exposed without being hidden by the semiconductor element (2b) stacked thereabove, and electrically connected to the metal thin film wiring layer. The semiconductor device can be manufactured in a smaller and thinner size and the number of manufacturing steps can be reduced by causing a plurality of semiconductor chips to be a vertically-stacked structure.

Abstract translation: 一种半导体器件，包括：半导体元件; 支撑基板（1）; 一个用于密封半导体元件（2a，2b）及其周边的绝缘材料层（4） 设置在绝缘材料层（4）中的金属薄膜布线层，其一部分暴露在外表面上; 和设置在所述绝缘材料层（4）中并与所述金属薄膜布线层电连接的金属过孔（9），其中所述半导体元件（2a，2b）设置为多个，并且各个半导体元件（2a，2b ）通过绝缘材料（4）堆叠，使得每个半导体元件（2a，2b）的电路表面面对金属薄膜布线层，并且每个半导体元件（2a）的电极焊盘被暴露而不被半导体隐藏 元件（2b）堆叠在其上面，并且电连接到金属薄膜布线层。 通过使多个半导体芯片成为垂直层叠结构，能够使半导体装置小型化，薄型化，并且能够减少制造工序。

公开(公告)号：EP2752873A2

公开(公告)日：2014-07-09

申请号：EP14162557.4

申请日：2013-02-28

Applicant: J-Devices Corporation

Inventor： Umeki, Akihiro ,  Hiruta, Yoichi

IPC: H01L25/03 ,  H01L25/065 ,  H01L21/66

CPC classification number: H01L23/28 ,  H01L21/56 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/34 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32155 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor module, having a semiconductor package, which is obtained by mounting and resin-sealing a semiconductor bare chip on a first package substrate; a semiconductor bare chip; and a second package substrate; wherein the semiconductor package is mounted on the second package substrate and the semiconductor bare chip is mounted on the semiconductor package, wherein the semiconductor package is bonded to the second package substrate at the resin surface and electrically connected to the second package substrate by wire bonding.

Abstract translation: 一种半导体模块，其具有半导体封装，该半导体封装通过在第一封装基板上安装并树脂密封半导体裸芯片而获得; 半导体裸芯片; 和第二封装衬底; 其中所述半导体封装件安装在所述第二封装件衬底上，并且所述半导体裸芯片安装在所述半导体封装件上，其中所述半导体封装件在所述树脂表面处接合到所述第二封装件衬底并且通过引线接合电连接到所述第二封装件衬底。

公开(公告)号：EP2634796A2

公开(公告)日：2013-09-04

申请号：EP12189403.4

申请日：2012-10-22

Applicant: J-Devices Corporation

Inventor： Sawachi, Shigenori ,  Yamagata, Osamu ,  Inoue, Hiroshi ,  Itakura, Satoru ,  Chikai, Tomoshige ,  Hori, Masahiko ,  Katsumata, Akio

IPC: H01L21/98 ,  H01L25/065

Abstract: A semiconductor device, comprising: a semiconductor element; a support substrate (1); an insulating material layer (4) for sealing the semiconductor element (2a, 2b) and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer (4), with a part thereof being exposed on an external surface; and metal vias (9) provided in the insulating material layer (4) and electrically connected to the metal thin film wiring layer, wherein the semiconductor element (2a, 2b) is provided in a plurality, and the respective semiconductor elements (2a, 2b) are stacked via an insulating material (4) such that a circuit surface of each semiconductor element (2a, 2b) faces the metal thin film wiring layer, and electrode pads of each semiconductor element (2a) are exposed without being hidden by the semiconductor element (2b) stacked thereabove, and electrically connected to the metal thin film wiring layer. The semiconductor device can be manufactured in a smaller and thinner size and the number of manufacturing steps can be reduced by causing a plurality of semiconductor chips to be a vertically-stacked structure.

Abstract translation: 一种半导体器件，包括：半导体元件; 支撑基板（1）; 用于密封半导体元件（2a，2b）的绝缘材料层（4）及其周边; 设置在绝缘材料层（4）中的金属薄膜布线层，其一部分露出在外表面上; 以及设置在所述绝缘材料层（4）中并电连接到所述金属薄膜布线层的金属通孔（9），其中所述半导体元件（2a，2b）设置为多个，并且所述半导体元件（2a，2b） ）通过绝缘材料（4）堆叠，使得每个半导体元件（2a，2b）的电路表面面向金属薄膜布线层，并且每个半导体元件（2a）的电极焊盘暴露而不被半导体隐藏 元件（2b），并且与金属薄膜布线层电连接。 半导体器件可以制造成更小和更薄的尺寸，并且可以通过使多个半导体芯片成为垂直堆叠的结构来减少制造步骤的数量。

公开(公告)号：EP2634796B1

公开(公告)日：2020-04-08

申请号：EP12189403.4

申请日：2012-10-22

Applicant: J-Devices Corporation

Inventor： Sawachi, Shigenori ,  Yamagata, Osamu ,  Inoue, Hiroshi ,  Itakura, Satoru ,  Chikai, Tomoshige ,  Hori, Masahiko ,  Katsumata, Akio

IPC: H01L23/538 ,  H01L21/98