公开(公告)号：JP2009246324A

公开(公告)日：2009-10-22

申请号：JP2008110972

申请日：2008-04-22

Applicant: Powertech Technology Inc ,  力成科技股▲ふん▼有限公司

Inventor： CHEN CHIN-TI

IPC: H01L23/28 ,  H01L21/56 ,  H01L23/50

CPC classification number: H01L23/4951 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05599

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor package structure having a reinforced lead structure. SOLUTION: This semiconductor package structure 100 includes: a carrier 101 having a plurality of leads, wherein each of the leads is composed of an inner lead 102 and an outer lead 104; a chip 200 arranged on the bottom surfaces of the inner leads; an electrical connecting structure 300; and a molding component 400. In the inner lead, a stair-like step part is bent outward from a horizontal part of the upper surface of the chip. The outer lead is extended outwardly horizontally from the inner lead, and thereby a height difference is formed between the outer lead and the chip. The height difference prevents the particles having intruded from contacting the lead and the chip at the same time in a packaging process to interfere with electric conduction of an element in the chip, and improves the electrical reliability of the chip after packaging. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 解决的问题：提供一种具有加强引线结构的半导体封装结构。 解决方案：该半导体封装结构100包括：具有多个引线的载体101，其中每个引线由内引线102和外引线104组成; 布置在内引线的底表面上的芯片200; 电连接结构300; 和模制部件400.在内引线中，阶梯状台阶部从芯片的上表面的水平部分向外弯曲。 外引线从内引线向外水平延伸，从而在外引线和芯片之间形成高度差。 高度差防止了在包装过程中同时侵入引线和芯片的颗粒干扰芯片中的元件的导电，并且提高了封装后芯片的电可靠性。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009231296A

公开(公告)日：2009-10-08

申请号：JP2008070841

申请日：2008-03-19

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： YU BING-SHUN ,  HONG JINWEI

IPC: H01L23/12

CPC classification number: H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/15311 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a heat radiation type multiple hole semiconductor package for preventing a built-in heat sink from being separated by reinforcing heat radiation properties and reducing the warpage of a substrate. SOLUTION: The heat radiation type multiple hole semiconductor package includes: the substrate 210; a chip 220; the built-in type heat sink 230; and a sealed body 240. The substrate 210 includes: an upper surface 211, a lower surface 212, and a plurality of positioning holes 213; the chip 220 is installed on the upper surface 211; and the built-in type heat sink 230 is stuck to the chip 220. The built-in type heat sink 230 includes a plurality of support leads 231 and a heat radiation surface 232, and the group of support leads 231 is inserted into the group of positioning holes 213. Since the group of positioning holes 213 is not fully filled into the group of support leads 231, a plurality of mold flow passages 241 are formed. The sealed body 240 is formed on the upper surface 211 to seal the chip 220 and the built-in type heat sink 230. By exposing the heat radiation surface 232 and filling the mold flow passage 241, the group of support leads 231 is covered. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种散热型多孔半导体封装，用于通过加强散热性能和减少基板的翘曲来防止内置的散热器被分离。 散热型多孔半导体封装包括：基板210; 芯片220; 内置式散热器230; 和密封体240.基板210包括：上表面211，下表面212和多个定位孔213; 芯片220安装在上表面211上; 并且内置型散热器230粘附到芯片220.内置型散热器230包括多个支撑引线231和散热表面232，并且该组支撑引线231插入到该组 定位孔213的一组定位孔213未被完全填充到一组支撑引线231中，形成多个模流通道241。 密封体240形成在上表面211上，以密封芯片220和内置型散热器230.通过暴露散热表面232并填充模具流动通道241，覆盖了一组支撑引线231。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009231295A

公开(公告)日：2009-10-08

申请号：JP2008070840

申请日：2008-03-19

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： CHEN CHIN-TI ,  HONG JINWEI ,  YU BING-SHUN ,  WANG CHIN-FA

IPC: H01L21/02 ,  H01L23/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device provided with a substrate identification code allowing quality control and an abnormality tracing without changing a using appearance.
SOLUTION: This semiconductor device is provided with a substrate 110, a chip 120 and the substrate identification code 130. The substrate 110 has an upper surface 111 and a lower surface 112, has a wiring layer 113 and a solder mask layer 114 formed on the lower surface 112 and further has a non-wiring region 115, and the solder mask layer 114 almost covers the wiring layer 113 and the non-wiring region 115. The chip 120 is installed on the upper surface 111 of the substrate 110, and the substrate identification code 130 is baked on the lower surface 112 of the substrate 110 by using a laser engraving method.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有允许质量控制和异常跟踪的基板识别码而不改变使用外观的半导体器件。 解决方案：该半导体器件设置有衬底110，芯片120和衬底识别码130.衬底110具有上表面111和下表面112，具有布线层113和焊料掩模层114 形成在下表面112上并且还具有非布线区域115，并且焊料掩模层114几乎覆盖布线层113和非布线区域115.芯片120安装在基板110的上表面111上 ，并且通过使用激光雕刻方法在基板110的下表面112上烘烤基板识别代码130。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009224726A

公开(公告)日：2009-10-01

申请号：JP2008070400

申请日：2008-03-18

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： HSIEH WAN JUNG ,  WANG CHIN-FA ,  CHEN CHIN-TI

IPC: H01L23/50

CPC classification number: H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/4899 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To provide a COL semiconductor package to avoid electrical short caused by wire bonding and to facilitate the layouts of the leads at a lower surface of a chip with smaller die pads or without die pad. SOLUTION: The COL semiconductor package primarily includes: a plurality of leadframe's leads 210; a chip 220; a plurality of bonding wires 230; an insulation tape 240; and an encapsulant 250. Each lead has a plurality of carrying bars 211, a plurality of bonding finger 212, and a plurality of connecting lines 213 for connecting the carrying bar with the bonding finger. The chip has a main surface 221 and a back surface 222, wherein a plurality of bonding pads 223 are disposed on the main surface and the back surface is attached to the carrying bars 210. The bonding pads 223 are connected to the bonding fingers 212 by the bonding wires 230, wherein at least one of the plurality of bonding wires 230 overpasses one of the connecting lines 213A without electrical connection. The insulation tape 240 is attached to the connecting lines 213. The encapsulant 250 encapsulates the chip 220, the bonding wires 230, the insulation tape 240, the bonding fingers 212, and the connecting lines 213. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供COL半导体封装以避免引线接合引起的电短路，并且便于在具有较小管芯焊盘或没有管芯焊盘的芯片的下表面处引线的布局。 解决方案：COL半导体封装主要包括：多个引线框引线210; 芯片220; 多个接合线230; 绝缘带240; 和密封剂250.每个引线具有多个承载杆211，多个接合指状物212和用于将承载杆与接合爪连接的多个连接线213。 芯片具有主表面221和后表面222，其中多个接合焊盘223设置在主表面上，并且后表面附接到传送杆210.接合焊盘223通过 接合线230，其中多个接合线230中的至少一个超过连接线213A中的一个而没有电连接。 绝缘胶带240附接到连接线213.密封剂250封装芯片220，接合线230，绝缘带240，接合指状物212和连接线213.版权所有（C）2010 ，JPO＆INPIT

公开(公告)号：JP2009200210A

公开(公告)日：2009-09-03

申请号：JP2008039711

申请日：2008-02-21

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： FAN WEN-JENG ,  LIU YI-LING

IPC: H01L23/12

CPC classification number: H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor package restraining warpage in the side of a substrate, preventing fracture in the substrate, and avoiding damage to the surface of a chip and the side, and to provide a substrate used for the semiconductor package. SOLUTION: The substrate 210 of the semiconductor package 200 includes a plurality of signal fingers 211, a dummy metal pattern 212, and at least one peripheral recessed groove 213 passing through the substrate 210. The dummy metal pattern 212 is extended to a position 213 of the peripheral recessed groove, and is electrically insulated from the signal finger 211. The chip 220 is installed on the substrate 210 and includes a plurality of bonding pads 221, 222, and electrically connects the bonding pad of the chip to the signal finger 211 of the substrate via an electric connection element 230. A sealing body 240 seals the electric connection element 230 and is filled into the peripheral recessed groove 213. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了提供在基板侧面抑制翘曲的半导体封装，防止基板的断裂，并且避免对芯片和侧面的损坏，并且提供用于半导体的基板 包。 解决方案：半导体封装200的衬底210包括多个信号指211，虚拟金属图案212和穿过衬底210的至少一个周边凹槽213。虚拟金属图案212延伸到 外周凹槽的位置213，与信号指211电绝缘。芯片220安装在基板210上，并且包括多个焊盘221,222，并将芯片的焊盘电连接到信号 通过电连接元件230的基板的指状物211.密封体240密封电连接元件230并填充到周边凹槽213中。版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009135193A

公开(公告)日：2009-06-18

申请号：JP2007308722

申请日：2007-11-29

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： IWATA TAKAO

IPC: H01L23/12 ,  H01L21/3205 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L2224/16145 ,  H01L2224/4813 ,  H01L2924/01019

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor chip device with a silicon through-hole that has superior resistance to stress to achieve a high-density electric connection when a chip is stacked or mounted, and hardly causes a short circuit, and to provide a manufacturing method thereof.
SOLUTION: The semiconductor chip device 200 includes: a chip 210 which has an active surface 211, a back surface 212, and a bonding pad 213 formed on the active surface 211; a rewiring layer 220 formed on the active surface 211 and having a rearrangement pad 221 to be connected to the bonding pad 213; a passivation layer 230 formed on the active surface 211 to cover the rewiring layer 220 and expose the rearrangement pad 221; the through-hole 240 formed in the rearrangement pad 221 and penetrating the chip 210; an insulating layer 250 formed in the through-hole 240; and flexible metal wiring 260 having a first end 261 and a second end 262, the first end 261 being bonded to the rearrangement pad 221 and the second end 262 passing through the through-hole 240 to project to the back surface 212.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了提供具有优异的耐应力的硅通孔的半导体芯片器件，以便在堆叠或安装芯片时实现高密度电连接，并且几乎不引起短路，并且 以提供其制造方法。 解决方案：半导体芯片器件200包括：芯片210，其具有形成在有源表面211上的有源表面211，后表面212和接合焊盘213; 形成在有源面211上并具有与接合焊盘213连接的重排焊盘221的再布线层220; 形成在有源表面211上以覆盖重新布线层220并暴露重排衬垫221的钝化层230; 形成在重排衬垫221中并穿透芯片210的通孔240; 形成在通孔240中的绝​​缘层250; 以及具有第一端261和第二端262的柔性金属布线260，第一端261接合到重排衬垫221，第二端262穿过通孔240突出到后表面212。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009099750A

公开(公告)日：2009-05-07

申请号：JP2007269635

申请日：2007-10-17

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： FAN WEN-JENG

IPC: H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a stackable semiconductor package which enhances durability of a product and suppresses crevice spreading.
SOLUTION: The semiconductor package has a chip carrier 210, a chip 220, and a plurality of lower bump sets 230. The chip carrier 210 has an upper surface 211 on which a plurality of transfer pads 213 are installed and a lower surface 212 where a plurality of circumscribed pads 214 are installed. The chip 220 is installed at or electrically connected to the chip carrier 210. The lower bump sets 230 are made to correspond to or installed at a circumscribed pad group 214. The lower bump sets 230 coupled to the respective circumscribed pads 214 are composed of a plurality of conductor columns 231 and 232, and a solder material filling gap is formed between adjacent conductor columns 231 and 232 of the same lower bump set 230.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供可提高产品的耐久性并抑制缝隙扩展的可堆叠半导体封装。 解决方案：半导体封装具有芯片载体210，芯片220和多个下凸块组230.芯片载体210具有上表面211，多个转移垫213安装在该上表面211上，下表面 212，其中安装有多个外接垫214。 芯片220安装在芯片载体210处或电连接到芯片载体210.下凸起组230被制成对应于或安装在外接垫组214上。耦合到各个外接垫214的下凸块组230由 多个导体柱231和232以及焊料填充间隙形成在相同的下凸块组230的相邻的导体柱231和232之间。（C）版权所有（C）2009，JPO＆INPIT

公开(公告)号：MY144696A

公开(公告)日：2011-10-31

申请号：MYPI20080410

申请日：2008-02-26

Applicant: POWERTECH TECHNOLOGY INC

Inventor： MING-YEN WU

IPC: G01R31/02

Abstract: A UNIVERSAL INSERT FOR CARRYING A BGA PACKAGE UNDER TEST PRIMARILY COMPRISES A MESHED BASE, AT LEAST A LATCH, AND A PLURALITY OF LIFT PINS. THE MESHED BASE HAS A 5 COMPONENT CAVITY, A MOUNTING SURFACE AND A PLURALITY OF ALIGNING BALL HOLES IN THE COMPONENT CAVITY WHERE THE ALIGNING BALL HOLES ARE ARRANGED IN AN ARRAY WITH EQUAL PITCH. THE LATCH IS DISPOSED INSIDE THE MESHED BASE TO FIRMLY HOLD BGA PACKAGE UNDER TEST. THE LIFT PINS ARE FLEXIBLY EXTENDED FROM THE PERIPHERIES OF THE MOUNTING SURFACE OF THE MESHED BASE. DURING PROBE TESTING, THE COMPONENT CAVITY 10 ACCOMMODATES THE BGA PACKAGE INSIDE, AT LEAST SOME OF THE ALIGNING BALL HOLES ARE ONE-ON-ONE ALIGNED TO A PLURALITY OF SOLDER BALLS OF THE BGA PACKAGE SO THAT THE SOLDER BALLS ARE EXPOSED FROM THE CORRESPONDING ALIGNING BALL HOLES ON THE MOUNTING SURFACE. THEREFORE, THE UNIVERSAL INSERT IS NOT LIMITED BY THE SUBSTRATE DIMENSION OF A BGA PACKAGE, NOR BY THE NUMBER OF SOLDER BALLS, NOR BY THE LAYOUT OF SOLDER BALLS AND CAN 15 HOLD VARIOUS BGA PACKAGES WITH SAME BALL PITCH BUT WITH DIFFERENT SPECIFICATIONS OF BGA PACKAGE.

公开(公告)号：SG148909A1

公开(公告)日：2009-01-29

申请号：SG2008017097

申请日：2008-02-28

Applicant: POWERTECH TECHNOLOGY INC

Inventor： WU MING-YEN

Abstract: UNIVERSAL INSERT TOOL FOR FIXING A BGA PACKAGE UNDER TEST A universal insert for carrying a BGA package under test primarily comprises a meshed base, at least a latch, and a plurality of lift pins. The meshed base has a component cavity, a mounting surface and a plurality of aligning ball holes in the component cavity where the aligning ball holes are arranged in an array with equal pitch. The latch is disposed inside the meshed base to firmly hold BGA package under test. The lift pins are flexibly extended from the peripheries of the mounting surface of the meshed base. During probe testing, the component cavity accommodates the BGA package inside, at least some of the aligning ball holes are one-on-one aligned to a plurality of solder balls of the BGA package so that the solder balls are exposed from the corresponding aligning ball holes on the mounting surface. Therefore, the universal insert is not limited by the substrate dimension of a BGA package, nor by the number of solder balls, nor by the layout of solder balls and can hold various BGA packages with same ball pitch but with different specifications of BGA package.

公开(公告)号：US20240347438A1

公开(公告)日：2024-10-17

申请号：US18632221

申请日：2024-04-10

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L24/94 ,  H01L25/0655 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2924/1815

Abstract: A package structure including a redistributed circuit structure, a plurality of chips, a second encapsulant, a plurality of supporting members, a first encapsulant, and a plurality of connection terminals are provided. The redistributed circuit structure has a first surface and a second surface opposite thereto. The chips are disposed on the second surface of the redistributed circuit structure. The second encapsulant is disposed on the second surface of the redistributed circuit structure and covers the chips. The supporting members are disposed on the first surface of the redistributed circuit structure. The first encapsulant is disposed on the first surface of the redistributed circuit structure and covers the supporting members. The connection terminals are connected to the supporting members.