公开(公告)号：JP2003332886A

公开(公告)日：2003-11-21

申请号：JP2003110812

申请日：2003-04-15

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド

Inventor： DARBEL NICOLAS ,  GUILLEY SYLVAIN

IPC: H03H17/02 ,  H04B1/707

CPC classification number: H03H17/0254

Abstract: PROBLEM TO BE SOLVED: To provide a digital matched filter in which power consumption is reduced, and a silicon area is reduced.
SOLUTION: The digital matched filter receives an input signal in a natural order. That input signal is then correlated against a code to produce filtered output signals. The filtered output signals, however, are produced from the correlation in a permuted order with respect to the received input signal. The code is the factorized first and second patterns. The filter includes: first filters for correlation with respect to the first code; second filters for correlation with respect to the second pattern; and a memory for storing the intermediate values produced by the correlative operation of the first filters. Certain ones of the intermediate values are thereafter selectively retrieved from the memory in response to an unique addressing scheme with respect to the correlation operations of each second filter. In accordance with the scheme, the retrieved intermediate values are reused in succeeding second filtering correlations.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种数字匹配滤波器，其中功耗降低，硅面积减小。

解决方案：数字匹配滤波器以自然的顺序接收输入信号。 然后该输入信号与代码相关以产生经滤波的输出信号。 然而，经滤波的输出信号是根据相对于所接收的输入信号的置换顺序的相关产生的。 代码是分解的第一和第二模式。 滤波器包括：用于与第一码相关的第一滤波器; 用于与第二图案相关的第二滤波器; 以及用于存储由第一滤波器的相关操作产生的中间值的存储器。 响应于关于每个第二滤波器的相关运算的唯一寻址方案，随后从存储器中选择性地检索某些中间值。 根据该方案，所检索的中间值在后续的第二滤波相关中重新使用。 版权所有（C）2004，JPO

公开(公告)号：JP2003330743A

公开(公告)日：2003-11-21

申请号：JP2003135968

申请日：2003-05-14

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド

Inventor： PARTHASARATHY SIVAGNANAM ,  RISSO ALESSANDRO

IPC: G06F11/00 ,  G06F9/445 ,  G06F11/36 ,  G06F12/00 ,  G06F12/12

CPC classification number: G06F9/328 ,  G06F8/66 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/126

Abstract: PROBLEM TO BE SOLVED: To provide a ROM patching device and method for patching a code in ROM (Read Only Memory) used in a data processing system for executing an instruction code in the ROM. SOLUTION: This ROM patching device includes (1) a patch buffer for storing a first replacement cache line containing a first new instruction suitable for replacing at least a portion of the codes in the ROM, (2) a lockable cache, and (3) a core processor logic operable to read from an associated memory a patch table containing a first table entry. The first table entry contains (1) the first new instruction, and (2) a first patch address identifying a first patched ROM address of the at least a portion of the code in the ROM. The core processor logic loads the first new instruction from the patch table into the patch buffer, stores the first replacement cache line from the patch buffer into the lockable cache, and locks the first replacement cache line into the lockable cache. COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种ROM修补装置和方法，用于修补在用于执行ROM中的指令码的数据处理系统中使用的ROM（只读存储器）中的代码。 解决方案：该ROM修补装置包括（1）补丁缓冲器，用于存储包含适于替换ROM中的至少一部分代码的第一新指令的第一替换高速缓存行，（2）可锁定高速缓存，以及 （3）核心处理器逻辑，可操作以从相关联的存储器读取包含第一表项的修补表。 第一表条目包含（1）第一新指令，以及（2）标识ROM中的代码的至少一部分的第一修补ROM地址的第一补丁地址。 核心处理器逻辑将补丁表中的第一个新指令加载到补丁缓冲区中，将补丁缓冲区中的第一个替换高速缓存行存储到可锁定高速缓存中，并将第一个替换高速缓存行锁定到可锁定高速缓存中。 版权所有（C）2004，JPO

公开(公告)号：JP2003317476A

公开(公告)日：2003-11-07

申请号：JP2003112529

申请日：2003-04-17

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド

Inventor： LAURENT DUANE GILES

IPC: H03K19/00 ,  G11C5/14 ,  G11C11/407

CPC classification number: G11C5/143

Abstract: PROBLEM TO BE SOLVED: To provide technique for monitoring reference voltage generated in a semiconductor memory device to simplify memory access operation.
SOLUTION: A pair of Schmitt trigger circuits are used. The first Schmitt trigger circuit detects that voltage appearing on an output of a reference voltage generator is dropped to a lower level than the minimum threshold voltage level. The second Schmitt trigger circuit detects that output voltage of the reference voltage generator exceeds the maximum threshold voltage level. This circuit can have a reset circuit giving initially the prescribed voltage level on an input of the Schmitt trigger circuit. The output circuit receives an output of each Schmitt trigger circuit and generates an output signal having a value indicating whether an output of the reference voltage generator is in a voltage range or not.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供用于监视在半导体存储器件中产生的参考电压的技术，以简化存储器存取操作。

解决方案：使用一对施密特触发器电路。 第一施密特触发电路检测到出现在参考电压发生器输出端的电压下降到比最小阈值电压电平更低的电平。 第二施密特触发电路检测到参考电压发生器的输出电压超过最大阈值电压电平。 该电路可以具有在施密特触发电路的输入端上给出初始规定电压电平的复位电路。 输出电路接收每个施密特触发电路的输出，并产生具有指示参考电压发生器的输出是否处于电压范围的值的输出信号。 版权所有（C）2004，JPO

公开(公告)号：JP2003045832A

公开(公告)日：2003-02-14

申请号：JP2002160030

申请日：2002-05-31

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド

Inventor： SPINNER CHARLES R III ,  NICKELL REBECCA A ,  GANDY TODD H

IPC: H01L21/3205 ,  H01L21/304 ,  H01L21/321 ,  H01L21/768

CPC classification number: H01L21/3212 ,  H01L21/7684

Abstract: PROBLEM TO BE SOLVED: To mitigate dishing during chemical mechanical polishing of a conformal tungsten layer. SOLUTION: A protective barrier layer, composed of a material such as titanium or titanium nitride, is formed on a conformal tungsten layer. Removal of the protective barrier layer by chemical mechanical polishing(CMP) is primarily mechanical rather than chemical. During subsequent CMP to pattern the tungsten layer, upper topological regions of the protective barrier layer are removed first, and the tungsten under those regions are exposed to be removed, while protective barrier layer regions over lower topological regions remain to prevent chemical attack to the underlying tungsten.

Abstract translation: 要解决的问题：在保形钨层的化学机械抛光期间减轻凹陷。 解决方案：在保形钨层上形成由诸如钛或氮化钛的材料构成的保护性阻挡层。 通过化学机械抛光（CMP）去除保护性阻隔层主要是机械的而不是化学的。 在随后的CMP中对钨层进行图案化，首先去除保护性阻挡层的上部拓扑区域，并且暴露出这些区域下面的钨被去除，同时保留在较低拓扑区域上的保护性阻挡层区域，以防止化学侵蚀到底层 钨。

公开(公告)号：JP2003016746A

公开(公告)日：2003-01-17

申请号：JP2002187168

申请日：2002-06-27

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド

Inventor： OZDEMIR HAKAN

IPC: G11B20/12 ,  G11B5/596 ,  G11B19/20 ,  G11B19/28 ,  G11B21/10

CPC classification number: G11B5/59633 ,  G11B19/20 ,  G11B19/28

Abstract: PROBLEM TO BE SOLVED: To provide a spin-up wedge relative to the spin-up of a data storage disk and to provide an improved servo circuit and a method to detect a corresponding servo-wedge.
SOLUTION: The servo circuit has a servo channel and a processor. The servo channel recovers servo data from a servo-wedge which identifies respective data sectors on the data storage disk. Relative to the spin-up of the disk, the processor detects a spin-up wedge related to one of the servo-wedge and then, detects the servo-wedge. When the servo-wedge is detected, a head positioning circuit reads positioning data from the servo-wedge and determines an initial position of a read/write head. By detecting both a spin-up wedge and a servo- wedge to determine the initial head position relative to a disk spin-up, the servo circuit frequently reduces the length of a spin-up wedge and increases the capacity of disk storage.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供相对于数据存储盘的旋转的旋转楔，并提供改进的伺服电路和检测相应的伺服楔的方法。 解决方案：伺服电路具有伺服通道和处理器。 伺服通道从伺服楔恢复伺服数据，该伺服楔识别数据存储盘上的相应数据扇区。 相对于盘的旋转，处理器检测与伺服楔中的一个相关的旋转楔，然后检测伺服楔。 当检测到伺服楔时，头定位电路从伺服楔读取定位数据并确定读/写头的初始位置。 通过检测自旋楔和伺服楔以确定相对于盘旋转的初始头位置，伺服电路经常减小旋转楔的长度并增加磁盘存储的容量。

公开(公告)号：JP2003006626A

公开(公告)日：2003-01-10

申请号：JP2002131644

申请日：2002-05-07

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド

Inventor： DANIEL A THOMAS

IPC: G06T1/00 ,  G06K9/00

CPC classification number: G06K9/00053

Abstract: PROBLEM TO BE SOLVED: To improve the durability and reliability of a fingerprint detector.
SOLUTION: The fingerprint detector having a smooth sensor surface for contact with a fingerprint includes capacitive sensor plates defining an array of sensor cells below the sensor surface and tungsten ESD protection grid lines surrounding each sensor cell. The sensor surface is defined by silicon carbide and includes silicon oxide filling cavities in the silicon carbide. The cavities inherently result from processing steps, including the removal of tungsten atop the silicon carbide that is used to define the grid lines. The cavities are filled with the oxide, and the surface made smooth by using chemical mechanical polishing, thus a scratch resistant surface is provided and the sensitivity of the capacitive sensor cells is improved.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提高指纹检测器的耐久性和可靠性。 解决方案：具有用于与指纹接触的平滑传感器表面的指纹检测器包括限定传感器表面下方的传感器单元阵列的电容式传感器板以及围绕每个传感器单元的钨ESD保护网格线。 传感器表面由碳化硅限定，并且在碳化硅中包括氧化硅填充腔。 这些空腔固有地来自加工步骤，包括去除用于限定网格线的碳化硅顶部的钨。 用氧化物填充空腔，通过使用化学机械抛光使表面变得光滑，从而提供耐刮擦表面，并提高电容式传感器单元的灵敏度。

公开(公告)号：JP2002368607A

公开(公告)日：2002-12-20

申请号：JP2002155519

申请日：2002-05-29

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド

Inventor： CHOW JAMES ,  WEN KENNY

IPC: H03H7/30 ,  H03L7/07 ,  H03L7/081

CPC classification number: H03L7/0805 ,  H03L7/07 ,  H03L7/0812

Abstract: PROBLEM TO BE SOLVED: To provide a method and system for a wide frequency data recovery, employing a precision closed loop delay line.
SOLUTION: A closed loop delay line system (700) includes a phase lock loop, that provides a phase lock output signal (715). A delay line (702) includes a clock input, a delay line output, and a delay line bias input. A bias signal, provided to the delay line bias input (727), adjusts the speed of the delay line (702). A phase detector (720) compares phase between a first timing signal input (704) and the delay line output (706). A bias adjust circuit mixes the phase compare output signal (725) and the phase lock output signal (715), to provide a combination bias signal (727) to the delay line (702). Additionally, the relative timing position of strobe outputs (743) from the delay line (702) can be individually adjusted.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种采用精密闭环延迟线的宽频数据恢复方法和系统。 解决方案：闭环延迟线系统（700）包括提供锁相输出信号（715）的锁相环。 延迟线（702）包括时钟输入，延迟线输出和延迟线偏置输入。 提供给延迟线偏置输入（727）的偏置信号调节延迟线（702）的速度。 相位检测器（720）比较第一定时信号输入（704）和延迟线输出（706）之间的相位。 偏置调整电路混合相位比较输出信号（725）和锁相输出信号（715），以向延迟线（702）提供组合偏置信号（727）。 此外，可以单独地调整来自延迟线（702）的选通脉冲输出（743）的相对定时位置。

公开(公告)号：JP6618528B2

公开(公告)日：2019-12-11

申请号：JP2017511150

申请日：2015-04-28

Applicant: ソイテック ,  Soitec ,  エスティーマイクロエレクトロニクス,インコーポレイテッド ,  STMicroelectronics,Inc

Inventor： アリベール,フレデリク ,  モラン,ピエール

IPC: H01L27/088 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/336 ,  H01L29/786 ,  H01L21/8234

公开(公告)号：JP2008289117A

公开(公告)日：2008-11-27

申请号：JP2008002131

申请日：2008-01-09

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッドSTMicroelectronics,Inc

Inventor： CHU LIWEN ,  HU WENDONG ,  VLANTIS GEORGE A

IPC: H04J13/06 ,  H04W84/14

CPC classification number: H04B1/715 ,  H04B1/7143 ,  H04B2001/7154 ,  H04W84/14

Abstract: PROBLEM TO BE SOLVED: To provide systems and methods for enhanced DFH (dynamic frequency hopping) among a plurality of WRAN (wireless regional area network) cells.
SOLUTION: A dynamic frequency hopping community (DFH community) is formed from a plurality of wireless regional area network (WRAN) cells, wherein each of the plurality of WRAN cells within the DFH community is a one-hop neighbor of the leader cell. The leader cell sets and distributes a hopping pattern for use among the WRAN cells, on the basis of, in part, the number of usable channels and whether a WRAN cell is shared by two groups in the DFH Community.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供多个WRAN（无线区域网络）小区之间用于增强的DFH（动态跳频）的系统和方法。 解决方案：从多个无线区域网络（WRAN）小区形成动态跳频社区（DFH community），其中DFH社区内的多个WRAN小区中的每一个都是领导者的一跳邻居 细胞。 领导单元基于部分可用信道的数量以及DFH群组中的两个群组共享一个WRAN小区来设置和分配在WRAN小区之间使用的跳频模式。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2006180509A

公开(公告)日：2006-07-06

申请号：JP2005368483

申请日：2005-12-21

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッドSTMicroelectronics,Inc

Inventor： DANG PHILIP P

IPC: H04N19/50

CPC classification number: H04N19/523 ,  H04N19/43 ,  H04N19/436

Abstract: PROBLEM TO BE SOLVED: To provide a method and system for fast implementation of subpixel interpolation. SOLUTION: A subpixel interpolator includes an input memory capable of storing video information formed from full pixels. The subpixel interpolator also includes at least one interpolation unit capable of performing subpixel interpolation to generate half-pixels and quarter-pixels in parallel. Multiple half-pixels and multiple quarter-pixels are generated concurrently during the subpixel interpolation. In addition, the subpixel interpolator includes an output memory capable of storing at least some of the full pixels, half-pixels, and quarter-pixels. In some embodiments, at least one interpolation unit includes a horizontal half-pixel interpolation unit, two vertical half-pixel interpolation units, and a quarter-pixel interpolation unit, all of which may operate in parallel. In particular embodiments, the interpolation units are formed from adders and shifters and do not include any multipliers. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种快速实现子像素插值的方法和系统。 解决方案：子像素插值器包括能够存储从全像素形成的视频信息的输入存储器。 子像素内插器还包括能够执行子像素内插以平行生成半像素和四分之一像素的至少一个内插单元。 在子像素插值期间同时产生多个半像素和多个四分之一像素。 此外，子像素内插器包括能够存储全像素，半像素和四分之一像素中的至少一些的输出存储器。 在一些实施例中，至少一个内插单元包括水平半像素内插单元，两个垂直半像素内插单元和四分之一像素内插单元，所有这些都可以并行操作。 在特定实施例中，插值单元由加法器和移位器形成，并且不包括任何乘法器。 版权所有（C）2006，JPO＆NCIPI