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    METHOD AND RECEIVER FOR RECEIVING A COMPOSITE SIGNAL
    52.
    发明公开
    METHOD AND RECEIVER FOR RECEIVING A COMPOSITE SIGNAL 有权
    用于接收复合信号的方法和接收器

    公开(公告)号：EP3092718A1

    公开(公告)日：2016-11-16

    申请号：EP14878244.4

    申请日：2014-09-26

    Applicant: Deere & Company

    Inventor： YU, Wei ,  KEEGAN, Richard, G.

    IPC: H04B1/00

    CPC classification number: H04B1/709 ,  G01S19/24 ,  G01S19/30 ,  H04B1/7075 ,  H04B1/70754 ,  H04B1/70755 ,  H04B1/7087 ,  H04B2201/70715 ,  H04B2201/70716 ,  H04B2201/70728 ,  H04B2201/7073 ,  H04L27/2663

    Abstract: A data processor selects a set of BOC correlations in accordance with a BOC correlation function for the sampling period if the primary amplitude exceeds or equals the secondary amplitude for the sampling period. The data processor selects a set of QBOC correlations in accordance with a QBOC correlation function for the sampling period if the secondary amplitude exceeds the primary amplitude for the sampling period. The data processor uses either the BOC correlation function or the QBOC correlation function, whichever with greater amplitude, at each sampling period for carrier tracking. Further, the data processor, through combining two sets of BOC correlations with different chip spacings provides an alternative unambiguous code acquisition of the received signal.

    Abstract translation: 如果主振幅超过或等于采样周期的次振幅，则数据处理器根据采样周期的BOC相关函数选择一组BOC相关性。 如果次级幅度超过采样周期的主振幅，则数据处理器根据采样周期的QBOC相关函数选择一组QBOC相关性。 数据处理器在每个采样周期使用BOC相关函数或QBOC相关函数（无论哪一个的幅度较大）来进行载波跟踪。 此外，数据处理器通过将两组BOC相关与不同芯片间隔相组合提供了对接收信号的替代明确代码获取。

    Clock and data recovery circuit with spread spectrum clocking synthesizer
    56.
    发明授权
    Clock and data recovery circuit with spread spectrum clocking synthesizer 有权

    公开(公告)号：US12003245B2

    公开(公告)日：2024-06-04

    申请号：US17902917

    申请日：2022-09-05

    Applicant: MEDIATEK INC.

    Inventor： Chien-Kai Kao ,  Yi-Hsien Cho

    IPC: H03L7/08 ,  H03L7/085 ,  H04B1/7073 ,  H04L7/00 ,  H04L7/033 ,  H04L27/227

    CPC classification number: H03L7/0807 ,  H03L7/085 ,  H04B1/7073 ,  H04L7/0025 ,  H04L7/0331 ,  H04L27/2271 ,  H04B2201/7073

    Abstract: The present invention provides a circuitry including a PLL and a CDR circuit, wherein the CDR circuit includes a phase detector, a loop filter, a SSC demodulator, a control code generator and a phase interpolator. The PLL is configured to generate a clock signal with SSC modulation and a SSC direction signal. The phase detector is configured to compare phases of an input signal and an output clock signal to generate a detection result, wherein the input signal is with SSC modulation. The loop filter is configured to filter the detection result to generate a filtered signal. The SSC demodulator is configured to receive the SSC direction signal to generate a control signal. The control code generator is configured to generate a control code according to the filtered signal and the control signal to control the phase interpolator to use the clock signal to generate the output clock signal.

    Clock and data recovery circuit
    57.
    发明授权
    Clock and data recovery circuit 有权

    公开(公告)号：US11742892B2

    公开(公告)日：2023-08-29

    申请号：US17734920

    申请日：2022-05-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Hsiang Lan ,  Cheng-Hsiang Hsieh

    IPC: H04L7/02 ,  H04B1/7085 ,  H04L7/00

    CPC classification number: H04B1/7085 ,  H04L7/0029 ,  H04B2201/7073

    Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

    COMMUNICATION SYSTEM EMPLOYING CHAOTIC SEQUENCE BASED FREQUENCY SHIFT KEYING SPREADING SIGNALS
    58.
    发明申请
    COMMUNICATION SYSTEM EMPLOYING CHAOTIC SEQUENCE BASED FREQUENCY SHIFT KEYING SPREADING SIGNALS 审中-公开

    公开(公告)号：US20180309477A1

    公开(公告)日：2018-10-25

    申请号：US15961731

    申请日：2018-04-24

    Applicant: Chaos Prime, Inc.

    Inventor： Alan Michaels

    IPC: H04B1/7075 ,  H04L27/20 ,  H04L27/12

    CPC classification number: H04B1/70754 ,  H04B1/707 ,  H04B2001/70724 ,  H04B2201/7073 ,  H04L27/122 ,  H04L27/2028 ,  H04L27/2035 ,  H04L27/2092

    Abstract: A candidate arbitrary-phase spread spectrum modulation technique that offers similar performance to spread continuous phase modulation (CPM) waveforms and additional capabilities for programming a chosen frequency domain spectra into the resulting spread spectrum signal. The proposed chaotic-FSK waveform is derived from high-order sequence-based spread spectrum signals, with multi-bit resolution chaos-based sequences defining incremental phase words, enabling real-time efficient generation of practically non-repeating waveforms. A result of the C-FSK formulation is a parameterized hybrid modulation capable of acting like a traditional sequence-based spread spectrum signal or a traditional frequency shift keying signal depending on chosen parameters. As such, adaptation in this modulation may be easily implemented as a time-varying evolution, increasing the security of the waveform while retaining many efficiently implementable receiver design characteristics of traditional PSK modulations.

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