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    Tunable quadrature phase shifter
    61.
    发明公开
    Tunable quadrature phase shifter 失效
    Abstimmbarer quadratur Phasenschieber

    公开(公告)号：EP0707379A1

    公开(公告)日：1996-04-17

    申请号：EP94202939.8

    申请日：1994-10-11

    Applicant: BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap

    Inventor： Sevenhans, Joannes Mathilda Josephus ,  Duvivier, Eric ,  Sallaerts, Daniel

    IPC: H03H11/22

    CPC classification number: H03H11/22

    Abstract: A tunable quadrature phase shifter including two branches each constituted by the cascade connection of a filter, an amplifier and a summing circuit, and two cross-connections constituted by amplifiers interconnecting the filter of one branch to the summing circuit of the opposite branch. An accurate 90 degrees phase shift between the two output signals is obtained by controlling the tail currents of the four amplifiers.
    The phase shifter used in mobile telecommunication transceivers may be easily and accurately tuned because the signals used in the summing circuits all have a similar amplitude. It is further adapted to operate with only 3 Volt battery supply as used in wireless phones.
    The bandwidth of the amplifiers is increased by using double differential pair amplifiers which behave as cascode arrangements.

    Abstract translation: 包括两个分支的可调谐正交移相器，每个分支由滤波器，放大器和求和电路的级联连接构成，以及由将一个分支的滤波器互连到相对分支的求和电路的放大器构成的两个交叉连接。 通过控制四个放大器的尾部电流，可以获得两个输出信号之间精确的90度相移。 用于移动电信收发机的移相器可以容易且准确地调整，因为在求和电路中使用的信号都具有相似的幅度。 它还适用于无线电话中使用的仅3伏电池供电。 通过使用作为共源共栅布置的双差分对放大器来增加放大器的带宽。

    Line impedance synthesis circuit
    63.
    发明公开
    Line impedance synthesis circuit 失效
    Impedanz-NachbildungsschaltungfürTeilnehmerleitung

    公开(公告)号：EP0703695A1

    公开(公告)日：1996-03-27

    申请号：EP94202727.7

    申请日：1994-09-22

    Applicant: BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap

    Inventor： Sevenhans, Joannes Mathilda Josephus ,  Sallaerts, Daniel

    IPC: H04M19/00

    CPC classification number: H04M19/005

    Abstract: A line impedance synthesis circuit for a telecommunication line circuit is described which is coupled to line terminals (AW,BW) of a telecommunication line and fed from first (GND) and second (VBAT) terminals of a voltage supply source. The line terminals (AW,BW) are coupled to these supply terminals via respective first and second impedance means which include a main path (A-B) of a first transistor circuit (K1A/K1B) shunted by the series connection of a resistance circuit (TRA/TRB) and a main path (A-B) of a second transistor circuit (K2A/K2B), control electrodes (CT) of the first (K1A/K1B) and second (K2A/K2B) transistor circuits being coupled to a same control output of a control circuit (AMPA,SUMA/AMPB,SUMB).

    Abstract translation: 描述了用于电信线路电路的线路阻抗合成电路，其被耦合到电信线路的线路终端（AW，BW）并且从电压源的第一（GND）和第二（VBAT）端子馈送。 线路端子（AW，BW）通过相应的第一和第二阻抗装置耦合到这些电源端子，第一和第二阻抗装置包括由电阻电路（TRA）的串联连接分流的第一晶体管电路（K1A / K1B）的主路径（AB） / TRB）和第二晶体管电路（K2A / K2B）的主路径（AB），第一（K1A / K1B）和第二（K2A / K2B）晶体管电路的控制电极（CT）耦合到相同的控制输出 的控制电路（AMPA，SUMA / AMPB，SUMB）。

    Electronic franking machine
    68.
    发明公开
    Electronic franking machine 失效
    Elektronische Frankiermaschine。

    公开(公告)号：EP0573701A1

    公开(公告)日：1993-12-15

    申请号：EP92201672.0

    申请日：1992-06-10

    Applicant: BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap

    Inventor： Guillaume, Benoît

    IPC: G07B17/02

    CPC classification number: G07B17/00661 ,  G07B2017/00564 ,  G07B2017/00669

    Abstract: A machine for franking mail documents (DO) and including a drive unit adapted to displace these documents successively along a detector device (DM) and a printer head mechanism (PH). The detector device detects the document and triggers the printer head mechanism to print a stamp on a predetermined printing area of the document. This electronic franking machine includes a variable delay unit (DC) which subsequently to the detection of a document delays the triggering of the printer head mechanism (PH) and thereby modifies the printing area on which a stamp will be printed. By disabling or enabling the variable delay unit (DC) such a stamp is printed either in the upper right corner area of the document or in an area at a different distance, e.g. of about 12 cm, from the right hand edge of the document respectively. The first case is suitable for printing stamps on envelopes, whereas the second case is used when stamps have to be printed on paper strips to be wrapped around mailed newspapers.

    Abstract translation: 一种用于印刷邮件文件（DO）的机器，并且包括适于沿着检测器装置（DM）和打印头机构（PH）逐级移位这些文件的驱动单元。 检测器装置检测文件并触发打印头机构在文档的预定打印区域上打印印章。 该电子封印机包括可变延迟单元（DC），其随后检测文档延迟打印机头机构（PH）的触发，从而修改打印区域。 通过禁用或启用可变延迟单元（DC），这样的印记可以打印在文档的右上角区域中，或打印在不同距离的区域中。 约12厘米，分别从文件的右手边缘。 第一种情况适用于在信封上印刷邮票，而第二种情况则用于邮票必须印在纸条上以包裹在邮寄的报纸上。

    ELECTRONIC DEVICES AND SIGNAL COMPARATOR USING SAME
    69.
    发明授权
    ELECTRONIC DEVICES AND SIGNAL COMPARATOR USING SAME 失效
    使用相同的电子设备和信号比较器

    公开(公告)号：EP0376953B1

    公开(公告)日：1993-09-29

    申请号：EP88905804.6

    申请日：1988-06-30

    Applicant: BELL TELEPHONE MANUFACTURING COMPANY NAAMLOZE VENNOOTSCHAP ,  ALCATEL N.V.

    Inventor： SEVENHANS, Joannes, Mathilde, Josephus ,  GUEBELS, Pierre-Paul, François, Maurice, Marie

    IPC: H03K3/356 ,  G05F3/24 ,  H03F3/45

    CPC classification number: H03K3/35613 ,  G05F3/242 ,  H03F3/45076 ,  H03F2200/331

    Abstract: The subjects of the present invention are a bistate device (ST), a current source (BS), a bistable device (FF) and an input circuit (IC) which are all associated to constitute a signal comparator. The bistate device (ST) is a Schmitt trigger which includes current control devices (N17, P13; N18, P14) to provide a current for counterbalancing the deviation of the construction parameters of the transistors so that the operation characteristics of this device remain identical from one process to another. The current source (BS) uses a current mirror configuration and is controlled via a branch coupled between the voltage supply terminals (VDD; VSS), two (N2, N3) of the four (N1 to N4) series connected transistors forming part of this branch have a greater Width-by-Length W/L channel parameter so that identical current sources (BS) may be produced on a large scale because the current (I5; II) supplied by the latter is then independent of the threshold voltages of the constituent transistors. The bistable device (FF) is a fliflop circuit which has differential commoned input and output terminals (T1; T2) and is used to associate the input circuit (IC) having a differential analog output and the bistate device (ST) having a differential digital input. This bistate device has its input/output terminals shunted by a MOS transistor (N14) at every high clock signal (CLK) by which the common voltage on its terminals is then half way between the supply voltages so that, when the state changes, these voltages have only to vary by half instead of the full voltage difference. This allows a faster switching of the bistable device. The input circuit (IC) is an high frequency differential input (I1; I2)/double ended output (T1; T2) circuit.

    COMMUNICATION SWITCHING SYSTEM
    70.
    发明授权
    COMMUNICATION SWITCHING SYSTEM 失效
    通信交换系统

    公开(公告)号：EP0401238B1

    公开(公告)日：1993-06-30

    申请号：EP89902206.5

    申请日：1988-12-24

    Applicant: BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap ,  ALCATEL N.V.

    Inventor： DE SOMER, Michel, Philemon, Madeleine

    IPC: H04J3/16 ,  H04L12/54

    CPC classification number: H04L12/5601 ,  H04J3/1682 ,  H04J2203/0003 ,  H04J2203/0089 ,  H04L12/6418 ,  H04L49/104 ,  H04L49/606 ,  H04L2012/5672 ,  H04L2012/6459

    Abstract: In this system STM (Synchronous Transfer Mode) and ATM (Asynchronous Transfer Mode) cell streams are supplied to corresponding STM and ATM switching exchanges STME and ATME via the cascade connection of a multiplexer (MUX), a transmission link (L1) and a demultiplexer (DMUX). The MUX and DMUX are each constituted by a switching element with a plurality of inputs (I1/2; 13) and outputs (03, 04/5) coupled to a common switching means (SB1, TM1; SB2, TM2) via respective receiver (RC1/3) and transmitter (TC1/3) circuits. The common switching means samples the input cell streams at a frequency at least equal to the sum of the time slot frequencies of the time frames of the input cell streams. The time frames of the input and output cell streams are phase synchronous and the sampling of the input cell streams is performed in a predetermined order. The cells of the resultant (STM/ATM) cell stream are supplied to the transmitter circuits in function of their destination.

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