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公开(公告)号：AU1418788A
公开(公告)日：1988-11-10
申请号：AU1418788
申请日：1988-04-05
Applicant: PRIME COMPUTER INC
Inventor： ALLISON ROBERT , LEFSKY BRIAN
IPC: G06F12/06
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公开(公告)号：DE3465398D1
公开(公告)日：1987-09-17
申请号：DE3465398
申请日：1984-01-20
Applicant: PRIME COMPUTER INC
Inventor： NELSON DALE H
Abstract: A power supply circuit having a higher power factor and decreased current crest factor. The circuit preferably comprises an input circuit for receiving an input AC voltage and rectifying this voltage and an output circuit for providing a DC output voltage. A pulse-width-modulation circuit intercouples between the input and output circuits and includes a controlled circuit adapted to pass input AC current in pulse-wide increments with the pulse-width varying in inverse proportion to the AC voltage. In this manner, when the instantaneous AC voltage is low, the pulse widths are wider and conversely when the voltage is high, the pulse widths are narrower. In one version of the invention, the pulse width modulation is carried out by a programmed variable ratio transformer. In one preferred embodiment of the present invention, the current spreading circuit is of a quasi cosecant type while in another preferred embodiment of the invention, there is a combination of pulse-width-modulation with a typical input filter circuit including an OR circuit at the output to provide the necessary combining.
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公开(公告)号：AT28955T
公开(公告)日：1987-08-15
申请号：AT84100583
申请日：1984-01-20
Applicant: PRIME COMPUTER INC
Inventor： NELSON DALE H
Abstract: A power supply circuit having a higher power factor and decreased current crest factor. The circuit preferably comprises an input circuit for receiving an input AC voltage and rectifying this voltage and an output circuit for providing a DC output voltage. A pulse-width-modulation circuit intercouples between the input and output circuits and includes a controlled circuit adapted to pass input AC current in pulse-wide increments with the pulse-width varying in inverse proportion to the AC voltage. In this manner, when the instantaneous AC voltage is low, the pulse widths are wider and conversely when the voltage is high, the pulse widths are narrower. In one version of the invention, the pulse width modulation is carried out by a programmed variable ratio transformer. In one preferred embodiment of the present invention, the current spreading circuit is of a quasi cosecant type while in another preferred embodiment of the invention, there is a combination of pulse-width-modulation with a typical input filter circuit including an OR circuit at the output to provide the necessary combining.
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公开(公告)号：CA1212161A
公开(公告)日：1986-09-30
申请号：CA447131
申请日：1984-02-09
Applicant: PRIME COMPUTER INC
Inventor： BAHR RICHARD G , HOGAN THOMAS C
Abstract: A communications network including a plurality of terminals coupled together to provide a unidirectional communications ring. Each of the terminals is adapted to transmit (at an associated fixed data rate) a digital signal to the next downstream terminal on the ring. Each terminal is adapted to receive a digital signal at the data rate associated with the next upstream terminal. In each local terminal, there is a detector for detecting the received synchronization packets and associated data packets are generated for transmission to the next downstream terminal on the ring at a predetermined fixed data rate associated with the local terminal. The data of each transmitted data packet matches bit for bit the data of the corresponding received data packet. The number of bits in the transmit synchronization packet differs from the number of bits in the associated received synchronization packet in a manner so that the data rate for the composite packet formed by the transmitted data packet and associated synchronization data packet corresponds to the transmit data rate for the terminal. The difference varies between predetermined minimum and maximum limits, and may be zero for two terminals having substantially the same transient bit rate.
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公开(公告)号：CA1207462A
公开(公告)日：1986-07-08
申请号：CA446951
申请日：1984-02-07
Applicant: PRIME COMPUTER INC
Inventor： BAHR RICHARD G , COHEN PAUL B
IPC: H04L12/407 , H04L12/433 , H04L11/14
Abstract: A token-passing, ring-based data communications network provides a distributive method and apparatus for detecting and regenerating a lost token. The method includes, after detection of the loss of the token, transmitting at a detecting node a data packet not including a token, the data packet uniquely identifying the transmitting node as the data source. Simultaneously, the transmitting node, after transmitting the tokenless data packet, strips all incoming data from the network. If the transmitted packet is successfully received by the transmitting node, a new token is generated by the node. If the packet is not received, the node defers to an arbitration method which includes delaying a next data packet transmission for a probabilistically determined period of time. The mean time upon which the probabilistic approach is based increases with each unsuccessful data packet transmission attempt.
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Patent Agency Ranking
公开(公告)号：EP0134620B1
公开(公告)日：1991-06-19
申请号：EP84303073.5
申请日：1984-05-08
Applicant: PRIME COMPUTER, INC.
Inventor： Jones, Walter A. , Jones, Paul R., Jr. , Ardini, Joseph L., Jr. , Papworth, David B.
IPC: G06F9/38
CPC classification number: G06F9/3889 , G06F9/3867
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67.发明公开
公开(公告)号：EP0287295A3
公开(公告)日：1990-08-08
申请号：EP88303195.7
申请日：1988-04-11
Applicant: PRIME COMPUTER, INC.
Inventor： Presant, Stephen D.
CPC classification number: G06F9/4881 , G06F9/5011 , G06F13/10 , G06F15/161
Abstract: A method for performing an input/output process containing a programmed input/output (PIO) instruction in a multiprocessor system including at least two processors each having an associated I/O bus with I/O devices connected thereto. The method comprises the steps of storing a unique address and a bus location for each I/O device in a device location table, determining the address of a referenced I/O device prior to performing the PIO instruction, reading the corresponding I/O bus location of the referenced I/O device from the device location table and executing the input/output process on the prescribed processor associated with the I/O bus to which the referenced I/O device is located. The method is used in conjunction with a task scheduler including a process control block for each scheduled process. When the PIO instruction references a device on the local I/O bus, the input/output process is executed normally. To execute the input/output process on a remote processor, a locked descriptor identifying the remote processor is placed in the process control block for that process. The input/output process is then scheduled for execution on the remote processor.
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公开(公告)号：EP0192420A3
公开(公告)日：1987-12-09
申请号：EP86300988
申请日：1986-02-13
Applicant: PRIME COMPUTER, INC.
Inventor： Irukulla, Suren , Patel, Bimal V
CPC classification number: G06F7/535 , G06F7/49 , G06F7/4917 , G06F7/5375
Abstract: The invention provides a method and apparatus for radix-p non-restoring division. The division process occurs in four phases. In a first phase, the input operands are transformed to produce a divisor lying in a designated numerical range. Next, a transitional phase involves generating an initial radix-p quotient digit from the transformed numerator. An iterative phase of the process generates successive partial remainders according to a recursive method. From the sign and a single radix-p digit of each of these partial remainders, the process generates a radix-β quotient digit. Further, a fourth phase, which may run concurrently with the transitional and iterative phases, involves accumulating succesively generated quotient digits to produce a final quotient value.
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公开(公告)号：EP0134620A3
公开(公告)日：1986-10-01
申请号：EP84303073
申请日：1984-05-08
Applicant: PRIME COMPUTER, INC.
Inventor： Jones, Walter A. , Jones, Paul R., Jr. , Ardini, Joseph L., Jr. , Papworth, David B.
IPC: G06F09/38
CPC classification number: G06F9/3889 , G06F9/3867
Abstract: A data processing system for processing a sequence of program instructions has two independent pipelines, an instruction pipeline and an execution pipeline. Each pipeline has a plurality of serially operating stages. The instruction stages read instructions from storage and form therefrom address data to be employed by the execution pipeline. The execution pipeline receives the address data and uses it for referencing stored data to be employed for execution of the program instructions. Both pipelines operate synchronously under the control of a pipeline control unit which initiates operation of at least one stage of the execution pipeline prior to completion of the instruction pipeline for a particular instruction. Thereby operation of at least one instruction stage and one execution stage of the respective pipelines overlap for each program instruction. The instruction and execution pipelines share high speed memory. The pipeline control unit can independently control the flow of instructions through the two pipelines. This is important for operation in conjunction with a microcode storage element which allows conditional branching and subroutine operation. Circuitry also detects pipeline collisions and exception conditions and delays or inhibits operation of one or more of the pipeline stages in response thereto. Under control of the pipeline control unit, one of the independent pipelines can operate while the other is halted. Further, a program . instruction flow prediction apparatus and method employ a high speed flow prediction storage element for predicting redirection of program flow prior to the time when the instruction has been decoded. Circuitry is further provided for updating the storage element, correcting erroneous branch and/or non-branch predictions, and accommodating instructions occurring on even or odd boundaries of the normally read double word instruction. Circuitry is further provided for updating the program flow in a single execution cycle so that no disruption to normal instruction sequencing occurs.
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公开(公告)号：EP0119004A3
公开(公告)日：1985-11-06
申请号：EP84300794
申请日：1984-02-08
Applicant: PRIME COMPUTER, INC.
Inventor： Bahr, Richard G. , Hogan, Thomas C.
CPC classification number: H04L12/422
Abstract: A ring communications network has a plurality of terminals coupled together to provide a unidirectional communications ring, each terminal being arranged to receive a first digital signal at a data rate associated with the next upstream terminal in the ring and to transmit a second digital signal at a transmit data rate which may be different from the data rate of the received signal. Each signal comprises data packets interleaved with synchronization packets of elastic length to achieve synchronization around the ring. Thus, each terminal has a synchronizing network (12) containing an electric clock generator (32) having a plurality of outputs each shifted in time by a different multiple of ⅛ times the period of a fixed transmit clock signal generated internally by a transmit clock generator (26). In effect, synchronization is achieved by a shallow discretely adjusted delay (FIFO) buffer and sample point readjustment network. The buffer is read at the fixed transmit data rate and loaded at that same rate until the period of elasticity is detected. Then the sample point is reselected to fall in the middle of a transmit bit window effectively changing the FIFO buffer depth.
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