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    Copper oxide monitoring by scatterometry/ellipsometry during nitride or BLOK removal in damascene process
    61.
    发明授权
    Copper oxide monitoring by scatterometry/ellipsometry during nitride or BLOK removal in damascene process 有权
    在大马士革过程中氮化物或BLOK去除期间通过散射测量/椭偏仪测量氧化铜

    公开(公告)号：US06934032B1

    公开(公告)日：2005-08-23

    申请号：US10261514

    申请日：2002-09-30

    Applicant: Ramkumar Subramanian ,  Steven C. Avanzino ,  Bharath Rangarajan ,  Bhanwar Singh

    Inventor： Ramkumar Subramanian ,  Steven C. Avanzino ,  Bharath Rangarajan ,  Bhanwar Singh

    IPC: C23F4/00 ,  G01N21/21 ,  H01L21/311 ,  G01N21/55 ,  C23F1/18 ,  H01L21/66

    CPC classification number: H01L21/31116 ,  C23F4/00 ,  G01N21/211

    Abstract: A system and methodology for monitoring and/or controlling a semiconductor fabrication process is disclosed. Scatterometry and/or ellipsometry based techniques can be employed to facilitate providing measurement signals during a damascene phase of the fabrication process. The thickness of layers etched away during the process can be monitored and one or more fabrication components and/or operating parameters associated with the fabrication component(s) can be adjusted in response to the measurements to achieve desired results, such as to mitigate the formation of copper oxide during etching of a copper layer, for example.

    Abstract translation: 公开了用于监测和/或控制半导体制造工艺的系统和方法。 可以采用基于散射法和/或椭偏仪的技术来促进在制造过程的镶嵌阶段期间提供测量信号。 可以监测在该过程中被蚀刻掉的层的厚度，并且可以响应于测量来调整与制造部件相关联的一个或多个制造部件和/或操作参数以实现期望的结果，例如减轻形成 例如在蚀刻铜层期间的氧化铜。

    Comprehensive integrated lithographic process control system based on product design and yield feedback system
    62.
    发明授权
    Comprehensive integrated lithographic process control system based on product design and yield feedback system 有权
    基于产品设计和产量反馈系统的综合光刻过程控制系统

    公开(公告)号：US06915177B2

    公开(公告)日：2005-07-05

    申请号：US10261569

    申请日：2002-09-30

    Applicant: Khoi A. Phan ,  Bhanwar Singh ,  Bharath Rangarajan ,  Ramkumar Subramanian

    Inventor： Khoi A. Phan ,  Bhanwar Singh ,  Bharath Rangarajan ,  Ramkumar Subramanian

    IPC: G03F7/20 ,  H01L21/66 ,  G06F19/00

    CPC classification number: G03F7/70525 ,  G03F7/70616 ,  G03F7/70858 ,  H01L22/20

    Abstract: The present invention provides systems and methods that facilitate performing fabrication process. Critical parameters are valued collectively as a quality matrix, which weights respective parameters according to their importance to one or more design goals. The critical parameters are weighted by coefficients according to information such as, product design, simulation, test results, yield data, electrical data and the like. The invention then can develop a quality index which is a composite “score” of the current fabrication process. A control system can then do comparisons of the quality index with design specifications in order to determine if the current fabrication process is acceptable. If the process is unacceptable, test parameters can be modified for ongoing processes and the process can be re-worked and re-performed for completed processes. As such, respective layers of a device can be customized for different specifications and quality index depending on product designs and yields.

    Abstract translation: 本发明提供了便于执行制造过程的系统和方法。 关键参数被统称为质量矩阵，其根据其对一个或多个设计目标的重要性来对各个参数进行加权。 关键参数根据产品设计，仿真，测试结果，产量数据，电气数据等信息对系数进行加权。 然后，本发明可以开发质量指数，其是当前制造过程的综合“评分”。 然后，控制系统可以将质量指标与设计规范进行比较，以便确定当前的制造过程是否可接受。 如果该过程是不可接受的，则可以对正在进行的过程修改测试参数，并且可以对完成的过程重新处理和重新执行该过程。 因此，根据产品设计和产量，可以针对不同的规格和质量指数定制装置的各个层。

    Contact etch resistant spacers
    63.
    发明申请
    Contact etch resistant spacers 审中-公开
    接触蚀刻隔离层

    公开(公告)号：US20050121738A1

    公开(公告)日：2005-06-09

    申请号：US10726380

    申请日：2003-12-03

    Applicant: Calvin Gabriel ,  Christopher Lyons ,  Marina Plat ,  Ramkumar Subramanian

    Inventor： Calvin Gabriel ,  Christopher Lyons ,  Marina Plat ,  Ramkumar Subramanian

    IPC: H01L21/60 ,  H01L31/107

    CPC classification number: H01L21/76897

    Abstract: An apparatus and a method of fabricating a semiconductor device including the steps of forming a gate dielectric layer on a semiconductor substrate; forming a gate electrode over the gate dielectric layer wherein the gate electrode defines a channel interposed between source/drain regions formed within an active region of the semiconductor substrate; and forming contact etch resistant spacers on sidewalls of the gate electrode and sidewalls of the gate dielectric layer, the contact etch resistant spacers are of a non-silicon oxide and a non-nitride material.

    Abstract translation: 一种制造半导体器件的装置和方法，包括以下步骤：在半导体衬底上形成栅介电层; 在所述栅极电介质层上形成栅电极，其中所述栅电极限定介于形成在所述半导体衬底的有源区内的源/漏区之间的沟道; 以及在所述栅电极的侧壁和所述栅介质层的侧壁上形成耐接触蚀刻间隔物，所述耐接触蚀刻间隔物为非氧化硅和非氮化物材料。

    Patterning for elliptical Vss contact on flash memory
    64.
    发明授权
    Patterning for elliptical Vss contact on flash memory 有权
    闪存上的椭圆形Vss接触图案化

    公开(公告)号：US06900124B1

    公开(公告)日：2005-05-31

    申请号：US10654739

    申请日：2003-09-03

    Applicant: Hung-eil Kim ,  Anna Minvielle ,  Christopher F. Lyons ,  Marina V. Plat ,  Ramkumar Subramanian

    Inventor： Hung-eil Kim ,  Anna Minvielle ,  Christopher F. Lyons ,  Marina V. Plat ,  Ramkumar Subramanian

    IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/8247 ,  H01L27/115

    CPC classification number: H01L27/11521 ,  H01L21/76802 ,  H01L27/115

    Abstract: A method of forming a contact in a flash memory device is disclosed. The method increases the depth of focus margin and the overlay margin between the contact and the stacked gate layers. A plurality of stacked gate layers are formed on a semiconductor substrate, wherein each stacked gate layer extends in a predefined direction and is substantially parallel to other stacked gate layers. An interlayer insulating layer is deposited over the plurality of stacked gate layers, and a contact hole is patterned between a first stacked gate layer of the plurality of stacked gate layers and a second stacked gate layer of the plurality of stacked gate layers. The contact hole is formed in an elongated shape, wherein a major axis of the contact hole is substantially parallel to the stacked gate layers. A conductive layer is deposited in the contact hole and excess conductive material is removed.

    Abstract translation: 公开了一种在闪速存储器件中形成触点的方法。 该方法增加了接触和层叠栅极层之间的焦距裕度和覆盖边缘的深度。 在半导体衬底上形成多个层叠的栅极层，其中每个堆叠的栅极层沿预定的方向延伸并且基本上平行于其它堆叠的栅极层。 层叠绝缘层沉积在多个堆叠的栅极层上，并且在多个堆叠的栅极层的第一堆叠的栅极层和多个堆叠的栅极层的第二叠层栅极层之间形成接触孔。 接触孔形成为细长形状，其中接触孔的长轴基本上平行于堆叠的栅极层。 导电层沉积在接触孔中，去除过量的导电材料。

    System for rapidly and uniformly cooling resist
    65.
    发明授权
    System for rapidly and uniformly cooling resist 有权
    系统快速均匀地冷却抗蚀剂

    公开(公告)号：US06889763B1

    公开(公告)日：2005-05-10

    申请号：US09707413

    申请日：2000-11-06

    Applicant: Ramkumar Subramanian ,  Bharath Rangarajan ,  Michael K. Templeton

    Inventor： Ramkumar Subramanian ,  Bharath Rangarajan ,  Michael K. Templeton

    IPC: F25B9/02 ,  H01L21/00 ,  F25B29/00

    CPC classification number: F25B9/02 ,  H01L21/67109 ,  H01L21/67248

    Abstract: Resist coated wafers are rapidly and uniformly cooled by a fluid that has been cooled through the Joule-Thompson effect. Fluid from a high pressure reservoir is vented into a chamber that contains the substrates. By varying the pressure difference between the reservoir and the chamber, the temperature of the cooling fluid entering the chamber can be controlled. By also controlling the flow rate through the chamber, the average temperature difference between the fluid in the chamber and the substrates may be limited, whereby more uniform cooling is obtained. While the chamber pressure is lower than that in the high pressure reservoir, the chamber pressure may still be substantially greater than atmospheric. An elevated chamber pressure raises the specific heat and residence time of the fluid in the chamber, which also promotes uniform cooling.

    Abstract translation: 抗蚀涂层的晶片由已经通过焦耳汤普森效应冷却的流体快速均匀地冷却。 来自高压储存器的流体被排放到包含基板的室中。 通过改变储存器和室之间的压差，可以控制进入室的冷却流体的温度。 通过控制通过室的流量，可以限制室中的流体与基板之间的平均温差，从而获得更均匀的冷却。 虽然室压力低于高压储罐中的室压力，但腔室压力仍然可能显着大于大气压。 室内压力提高了流体在室内的比热和停留时间，这也促进了均匀的冷却。

    Lithography contrast enhancement technique by varying focus with wavelength modulation
    68.
    发明授权
    Lithography contrast enhancement technique by varying focus with wavelength modulation 有权
    通过波长调制改变焦点的平版印刷对比度增强技术

    公开(公告)号：US06829040B1

    公开(公告)日：2004-12-07

    申请号：US10703643

    申请日：2003-11-07

    Applicant: Jongwook Kye ,  Ivan Lalovic ,  Christopher F. Lyons ,  Ramkumar Subramanian

    Inventor： Jongwook Kye ,  Ivan Lalovic ,  Christopher F. Lyons ,  Ramkumar Subramanian

    IPC: G03B2742

    CPC classification number: G03F7/70575 ,  G03F7/703 ,  G03F7/70333

    Abstract: A projection lithography system exposes a photo sensitive material on a surface of a semiconductor substrate that includes surface height variations between a high level and a low level. The system comprises an illumination source projecting illumination within a narrow wavelength band centered about a nominal wavelength on an optic path towards the substrate during an exposure period. A wavelength modulation system within the optic path comprises means for chromatically separating the narrow wavelength band into at least two sub-bands, the first sub-band being smaller than the narrow wavelength band and centered about a first sub-band wavelength and the second sub-band being smaller than the narrow wavelength band and centered about a second sub-band wavelength and means for passing each of the first sub-band and the second sub-band during distinct time periods within the exposure period.

    Abstract translation: 投影光刻系统在半导体衬底的表面上曝光感光材料，其包括高电平和低电平之间的表面高度变化。 该系统包括照射源，其在曝光期间内以在光路上朝着衬底的标称波长为中心的窄波长带内投射照明。 光路内的波长调制系统包括用于将窄波段色带分离成至少两个子带的装置，第一子带小于窄波段并以第一子带波长为中心，第二子带 带窄于窄波长带并以第二子带波长为中心，以及用于在曝光周期内的不同时间段内通过第一子带和第二子带中的每一个的装置。

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