公开(公告)号：US09223996B2

公开(公告)日：2015-12-29

申请号：US13751628

申请日：2013-01-28

Applicant: STMicroelectronics S.A.

Inventor： Albert Martinez ,  William Orlando

IPC: G06F11/30 ,  G06F21/62 ,  G06F12/14 ,  G06F21/52 ,  G06F21/79 ,  G06F21/60

CPC classification number: G06F21/62 ,  G06F12/1408 ,  G06F12/1483 ,  G06F21/52 ,  G06F21/602 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2221/033 ,  G06F2221/2105

Abstract: A method for loading a program, contained in at least a first memory, into a second memory accessible by an execution unit, in which the program is in a cyphered form in the first memory, a circuit for controlling the access to the second memory is configured from program initialization data, instructions of the program, and at least initialization data being decyphered to be transferred into the second memory after configuration of the circuit.

Abstract translation: 一种用于将包含在至少第一存储器中的程序加载到执行单元可访问的第二存储器中的方法，其中程序处于第一存储器中的加密形式，用于控制对第二存储器的访问的电路是 由程序初始化数据，程序的指令，以及至少初始化数据被解密以在电路配置之后被传送到第二存储器中。

公开(公告)号：US09117805B2

公开(公告)日：2015-08-25

申请号：US14169913

申请日：2014-01-31

Applicant: STMicroelectronics S.A. ,  STMicroelectronics (Crolles 2) SAS ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： Heimanu Niebojewski ,  Yves Morand ,  Cyrille Le Royer

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L29/49 ,  H01L21/28008 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4925 ,  H01L29/4991 ,  H01L29/6653

Abstract: A MOS transistor including, above a gate insulator, a conductive gate stack having a height, a length, and a width, this stack having a lower portion close to the gate insulator and an upper portion, wherein the stack has a first length in its lower portion, and a second length shorter than the first length in its upper portion.

Abstract translation: 一种MOS晶体管，包括在栅极绝缘体上方的具有高度，长度和宽度的导电栅极堆叠，该堆叠具有靠近栅绝缘体的下部和上部，其中堆叠具有第一长度 下部，并且在其上部比第一长度短的第二长度。

公开(公告)号：US09099604B2

公开(公告)日：2015-08-04

申请号：US13858481

申请日：2013-04-08

Applicant: STMicroelectronics S.A. ,  STMicroelectronics (Crolles 2) SAS

Inventor： François Roy ,  Lucile Broussous ,  Julien Michelot ,  Jean-Pierre Oddou

IPC: H01L21/00 ,  H01L31/18 ,  H01L27/146

CPC classification number: H01L31/18 ,  H01L27/14605

Abstract: A method for manufacturing an image sensor, including the successive steps of: forming columns of a semiconductor material; forming one or several pixels at a first end of each of the columns; and deforming the structure so that the second ends of each of the columns come closer to each other or draw away from each other to form a surface in the shape of a polyhedral cap.

Abstract translation: 一种用于制造图像传感器的方法，包括以下连续步骤：形成半导体材料的列; 在每个列的第一端形成一个或几个像素; 并且使结构变形使得每个柱的第二端彼此靠近或彼此拉开以形成多面体盖的形状的表面。

公开(公告)号：US09012957B2

公开(公告)日：2015-04-21

申请号：US14017024

申请日：2013-09-03

Applicant: STMicroelectronics S.A.

Inventor： Vincent Quenette

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7851

Abstract: A MOS transistor including a U-shaped channel-forming semiconductor region and source and drain regions having the same U shape located against the channel-forming region on either side thereof, the internal surface of the channel-forming semiconductor region being coated with a conductive gate, a gate insulator being interposed.

Abstract translation: 一种MOS晶体管，包括U形沟道形成半导体区域和具有相同U形的源极和漏极区域，其位于其任一侧上的沟道形成区域，沟道形成半导体区域的内表面涂覆有导电 栅极，插入栅极绝缘体。

公开(公告)号：US08963273B2

公开(公告)日：2015-02-24

申请号：US14247084

申请日：2014-04-07

Applicant: STMicroelectronics S.A. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Michel Marty ,  François Roy ,  Jens Prima

IPC: H01L31/00 ,  H01L27/146

CPC classification number: H01L27/1464 ,  H01L27/1463 ,  H01L27/14683 ,  H01L27/14687 ,  H01L27/14689

Abstract: A method for forming a back-side illuminated image sensor, including the steps of: a) forming, from the front surface, doped polysilicon regions, of a conductivity type opposite to that of the substrate, extending in depth orthogonally to the front surface and emerging into the first layer; b) thinning the substrate from its rear surface to reach the polysilicon regions, while keeping a strip of the first layer; c) depositing, on the rear surface of the thinned substrate, a doped amorphous silicon layer, of a conductivity type opposite to that of the substrate; and d) annealing at a temperature capable of transforming the amorphous silicon layer into a crystallized layer.

Abstract translation: 一种用于形成背面照明图像传感器的方法，包括以下步骤：a）从前表面形成与衬底相反的导电类型的掺杂多晶硅区域，其垂直于正面延伸， 进入第一层; b）使衬底从其后表面变薄到达多晶硅区域，同时保持第一层的条带; c）在所述薄化衬底的后表面上沉积与所述衬底相反的导电类型的掺杂非晶硅层; 和d）在能够将非晶硅层转变成结晶层的温度下退火。

公开(公告)号：US08907373B2

公开(公告)日：2014-12-09

申请号：US13628614

申请日：2012-09-27

Applicant: STMicroelectronics S.A.

Inventor： Philippe Galy ,  Jean Jimenez ,  Johan Bourgeat ,  Boris Heitz

IPC: H01L29/74 ,  H01L31/111 ,  H01L29/788 ,  H01L23/62 ,  H01L29/747 ,  H01L27/02

CPC classification number: H01L27/0262 ,  H01L29/747

Abstract: A protection device includes a triac and triggering units. Each triggering unit is formed by a MOS transistor configured to operate at least temporarily in a hybrid operating mode and a field-effect diode. The field-effect diode has a controlled gate that is connected to the gate of the MOS transistor.

Abstract translation: 保护装置包括三端双向可控硅开关元件和触发单元。 每个触发单元由配置成至少在混合操作模式中暂时操作的MOS晶体管和场效应二极管形成。 场效应二极管具有连接到MOS晶体管的栅极的受控栅极。

公开(公告)号：US08877600B2

公开(公告)日：2014-11-04

申请号：US14104903

申请日：2013-12-12

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics S.A. ,  STMicroelectronics, Inc. ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： Claire Fenouillet-Beranger ,  Stephane Denorme ,  Nicolas Loubet ,  Qing Liu ,  Emmanuel Richard ,  Pierre Perreau

IPC: H01L21/20 ,  H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/84 ,  H01L27/1207

Abstract: A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.

Abstract translation: 一种制造混合SOI /体基板的方法，包括以下步骤：在绝缘层上在单晶半导体衬底上从包括称为SOI层的单晶半导体层的SOI晶片开始; 在SOI层上沉积至少一个掩模层，并形成与掩模层，SOI层和绝缘层交叉的开口，以到达衬底; 通过选择性外延和部分蚀刻步骤的重复交替生长半导体材料; 以及蚀刻围绕填充有半导体材料的所述开口的绝缘沟槽，同时在开口的周边向内侵入。

公开(公告)号：US20140170834A1

公开(公告)日：2014-06-19

申请号：US14104903

申请日：2013-12-12

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives ,  STMicroelectronics, Inc. ,  STMicroelectronics S.A.

Inventor： Claire Fenouillet-Beranger ,  Stephane Denorme ,  Nicolas Loubet ,  Qing Liu ,  Emmanuel Richard ,  Pierre Perreau

IPC: H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/84 ,  H01L27/1207

Abstract: A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.

Abstract translation: 一种制造混合SOI /体基板的方法，包括以下步骤：在绝缘层上在单晶半导体衬底上从包括称为SOI层的单晶半导体层的SOI晶片开始; 在SOI层上沉积至少一个掩模层，并形成与掩模层，SOI层和绝缘层交叉的开口，以到达衬底; 通过选择性外延和部分蚀刻步骤的重复交替生长半导体材料; 以及蚀刻围绕填充有半导体材料的所述开口的绝缘沟槽，同时在开口的周边向内侵入。

公开(公告)号：US20040264250A1

公开(公告)日：2004-12-30

申请号：US10789449

申请日：2004-02-26

Applicant: STMicroelectronics S.A.

Inventor： Sebastien Zink ,  Bruno Leconte ,  Paola Cavaleri

IPC: G11C016/04

CPC classification number: G11C16/3436 ,  G11C16/04 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/50004

Abstract: An electrically erasable and programmable memory includes memory cells and a verify-program device. The memory also comprises an erase verify device arranged for supplying an erase verify signal having a determined value when a datum read in a memory cell during a first verify-program cycle has an erase logic value. Application particularly to performing a blank verify test in serial input/output Flash memories.

Abstract translation: 电可擦除和可编程存储器包括存储器单元和验证程序设备。 存储器还包括擦除验证装置，其被布置为当在第一验证程序周期期间在存储器单元中读取的数据具有擦除逻辑值时，提供具有确定值的擦除验证信号。 特别适用于在串行输入/输出闪存中执行空白验证测试。

公开(公告)号：US20040264228A1

公开(公告)日：2004-12-30

申请号：US10717223

申请日：2003-11-19

Applicant: STMicroelectronics S.A.

Inventor： Richard Ferrant

IPC: G11C017/00

CPC classification number: G11C7/067 ,  G11C17/123

Abstract: The invention concerns a ROM circuit (40) comprising columns of storage cells, each column being connected to a bit site (BLi, BLinull1), wherein the columns are arranged in groups of two adjacent columns, each column of a group capable of being selectively activated relative to the other column of the group, thereby enabling the elimination of a connection to the ground of columns and the design of efficient reading amplifiers.