公开(公告)号：JP2004280818A

公开(公告)日：2004-10-07

申请号：JP2004069739

申请日：2004-03-11

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド STMicroelectronics,Inc

Inventor： TOURNEMILLE JEROME ,  TAMAGNO DAVID

IPC: G06F11/28 ,  G06F13/38 ,  G06F17/50 ,  G06K17/00

CPC classification number: G06F17/5022

Abstract: PROBLEM TO BE SOLVED: To provide a system and a method for simulating a USB smart card. SOLUTION: The system and the method for simulating a universal serial bus (USB) smart card device connected with a USB host device for development and debugging are provided and it includes a computer simulator and a USB host device with a host controller operatively connected along a communication link with the computer simulator for transmitting or receiving data packets to or from the computer simulator. A microcontroller is located between the computer simulator and the USB host device and translates the data packets into a USB protocol used by the USB host device and defined by the computer simulator. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供用于模拟USB智能卡的系统和方法。 解决方案：提供了用于模拟与USB主机设备进行开发和调试的通用串行总线（USB）智能卡设备的系统和方法，并且其包括计算机模拟器和具有主机控制器的USB主机设备 沿着与计算机模拟器的通信链路连接，用于向计算机模拟器发送数据分组或从计算机模拟器接收数据分组。 微控制器位于计算机模拟器和USB主机设备之间，并将数据分组转换为由USB主机设备使用并由计算机模拟器定义的USB协议。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004228089A

公开(公告)日：2004-08-12

申请号：JP2004013433

申请日：2004-01-21

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド STMicroelectronics,Inc

Inventor： LO PRIORE STEFANO ,  PALMIERI MICHELE ,  MASTROMATTEO UBALDO

IPC: H01M4/86 ,  H01M4/88 ,  H01M4/94 ,  H01M8/00 ,  H01M8/02 ,  H01M8/10 ,  H01M8/14 ,  H01M8/24

CPC classification number: H01M8/241 ,  H01M4/8626 ,  H01M8/0247 ,  H01M8/1007 ,  Y02P70/56

Abstract: PROBLEM TO BE SOLVED: To provide a micro fuel cell capable of supplying sufficient power while maintaining structural reliability, and a method of manufacturing the same. SOLUTION: The micro fuel cell 30 includes a substrate 32 and a plurality of outwardly extending PEM separators 34 spaced from each other to define positive and negative micro fluid channels 36 and 38. A positive catalyst/electrode serves as the lining of at least part of the positive micro fluid channel 36, and a negative catalyst/electrode serves as the lining of at least part of the negative micro fluid channel 38. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004194343A

公开(公告)日：2004-07-08

申请号：JP2003415101

申请日：2003-12-12

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド STMicroelectronics,Inc

Inventor： HUANG LUN BIN ,  RICHARDSON NICHOLAS ,  RAJGOPAL SURESH

IPC: H04L12/56

CPC classification number: H04L45/00 ,  H04L45/54 ,  H04L45/7457

Abstract: PROBLEM TO BE SOLVED: To provide a path compression optimization system and method therefor. SOLUTION: The path optimization system and method for eliminating single entry trie tables, which are used in a pipeline network search engine of a router, are provided. This system embeds in a parent trie table (1) path compression patterns having common prefix bits of a data packet and (2) skip counts indicating the length of the path compression patterns. The network search engine uses the path compression patterns and the skip counts to eliminate single entry trie tables from a data structure. Each path compression pattern is processed one stride at a time in subsequent pipeline stages of the network search engine. The elimination of unnecessary single entry trie tables reduces memory space, power consumption, and the number of memory accesses required for traversing the data structure. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004194319A

公开(公告)日：2004-07-08

申请号：JP2003408480

申请日：2003-12-08

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド STMicroelectronics,Inc

Inventor： HUANG LUN BIN ,  RICHARDSON NICHOLAS ,  RAJGOPAL SURESH

IPC: H04L12/56 ,  G06F17/30

CPC classification number: H04L45/54

Abstract: PROBLEM TO BE SOLVED: To provide an improved multi-bit trie network search engine and an operating method thereof. SOLUTION: The multi-bit trie network search engine is realized by the number of pipeline logic units corresponding to the number of longest prefix strides, and a combination of memory blocks for holding prefix tables. Each of the pipeline units is limited to one memory access, and the end point within the pipeline logic unit chain is variable to deal with prefixes having different lengths. The memory blocks are coupled to the pipeline logic units by a mesh type crossbar and form a combination of virtual memory banks, and memory blocks in arbitrary given physical memory banks may be allocated to a virtual memory bank for arbitrary specified pipeline logic unit. An embedded type programmable processor manages insertion and deletion of route in the prefix tables together with configuration of the virtual memory banks. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004164650A

公开(公告)日：2004-06-10

申请号：JP2003385620

申请日：2003-11-14

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド STMicroelectronics,Inc

Inventor： JAIN MANISH ,  ALINI ROBERTO

IPC: G11B20/10 ,  G05F1/10 ,  G11B5/02 ,  G11B5/09 ,  G11B19/00

CPC classification number: G11B19/00 ,  G11B19/2063

Abstract: PROBLEM TO BE SOLVED: To provide an improved system and method for voltage regulation.
SOLUTION: A voltage regulator includes an output node, and first and second regulator circuits. The first regulator circuit generates a first regulated voltage on the output node when a supply voltage equals or exceeds a predetermined threshold, and the second regulator circuit generates a second regulated voltage on the output node when the supply voltage is less than the predetermined threshold.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004152305A

公开(公告)日：2004-05-27

申请号：JP2003370500

申请日：2003-10-30

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド STMicroelectronics,Inc

Inventor： KARIM FARAYDON O

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/4843 ,  G06F9/30098 ,  G06F9/3851

Abstract: PROBLEM TO BE SOLVED: To provide an improved processing architecture for supporting a high processing condition and a high communication condition.
SOLUTION: This hyper-processor includes a control processor for controlling a task executed by a plurality of processor cores, and each processor core can include a plurality of execution units or special hardware units. The control processor schedules the tasks according to a control thread to the task including a hardware context generated in a compile period and including a register file, a program counter and a status bit for each task. The task is dispatched to the processor core or the special hardware unit for parallel, sequential, out-of-order or speculative execution. A universal register file includes data processed by the task. A mutual connection body mutually connects at least the processor core and the special hardware units with each other and with the universal register file to enable each node to communicate with other nodes.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004133939A

公开(公告)日：2004-04-30

申请号：JP2003349925

申请日：2003-10-08

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド STMicroelectronics,Inc

Inventor： RIZZO DAVIDE ,  COLAVIN OSWALD

IPC: G06F7/02 ,  G06F7/24 ,  G06F17/30

CPC classification number: G06F17/30985 ,  G06F7/026 ,  G06F7/24 ,  G06F2207/226

Abstract: PROBLEM TO BE SOLVED: To improve a reconfigurable processing device and to improve a resource manager for use in a reconfigurable processing device.
SOLUTION: A data sorting apparatus includes (1) a storage sorter that sorts a data set according to a defined criterion, and (2) a query mechanism that receives intermediate sorted data values from the storage sorter and compares the intermediate sorted data values to at least one key value. The storage sorter has a priority queue for sorting the data set, wherein the priority queue has M processing elements. The query mechanism receives the intermediate sorted data values from the M processing elements. The query mechanism includes a plurality of comparison circuits, each circuit capable of detecting if one of the intermediate sorted data values is equal to at least one key value or, if no match exists, extracting the minimal value greater than (or less than according to the defined criterion) at least one key value.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004133899A

公开(公告)日：2004-04-30

申请号：JP2003271791

申请日：2003-07-08

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド STMicroelectronics,Inc

Inventor： HILL JOHN P

IPC: G06F1/06 ,  G06F1/04

CPC classification number: G06F1/04

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit for using a high-frequency timing reference generator from a high-speed serial interface for providing clocking and timing conditions for the integrated circuit. SOLUTION: In a timing mechanism, the need for a phase locked loop (PLL) macro cell for providing a timing reference and a timing signal in an IC is removed. The IC is suitably used as a disk drive integrated circuit including DSPs, memories, data path controllers, data interfaces, custom macro cells, and DSP peripherals. The high-speed serial interface is suitably a Serial ATA (SATA), a universal serial bus (USB), a fiber channel, or a Serial Attached SCSI (SAS). COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种用于使用来自高速串行接口的高频定时参考发生器的集成电路，用于为集成电路提供时钟和定时条件。 解决方案：在定时机制中，消除了在IC中提供定时参考和定时信号的锁相环（PLL）宏小区的需要。 该IC适用于包括DSP，存储器，数据路径控制器，数据接口，定制宏单元和DSP外设的磁盘驱动器集成电路。 高速串行接口适用于串行ATA（SATA），通用串行总线（USB），光纤通道或串行连接SCSI（SAS）。 版权所有（C）2004，JPO

公开(公告)号：JP2004015060A

公开(公告)日：2004-01-15

申请号：JP2003158930

申请日：2003-06-04

Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド STMicroelectronics,Inc

Inventor： ROY ANIRBAN ,  FASOLI LUCA

IPC: H01L21/82 ,  G11C14/00 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L27/118 ,  H01L29/788 ,  H01L29/792 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/1736 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11803

Abstract: PROBLEM TO BE SOLVED: To provide an improved programmable logic device (PLD) and its manufacturing method.
SOLUTION: The PLD according to the present invention has an array comprising a plurality of PLD cells. Each of the PLD cells has programmable transistors and selective transistors. The PLD array is divided into at least one first area and at least one second area which is located adjacent to the at least one first area. The first area includes programmable transistors, and the second area includes selective transistors.
COPYRIGHT: (C)2004,JPO

公开(公告)号：TW201442121A

公开(公告)日：2014-11-01

申请号：TW102145372

申请日：2013-12-10

Applicant: 意法半導體公司 ,  STMICROELECTRONICS, INC. ,  國際商業機械公司 ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： 柳青 ,  LIU, QING ,  王俊利 ,  WANG, JUNLI

IPC: H01L21/336 ,  H01L21/28

CPC classification number: H01L21/823431 ,  H01L21/02112 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/82 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6681

Abstract: 本發明說明了一種用於製造具有使鰭與基板絕緣的絕緣層的鰭式場效電晶體(finFET)裝置之方法。該絕緣層可防止沒有該絕緣層時將流經該基板中之塊狀半導體材料之漏電流。可以塊狀半導體基板開始製造該結構，而不需要絕緣層上覆半導體基板。可以磊晶生長法形成鰭結構，因而可改善該等裝置中之鰭高度的一致性。

Abstract in simplified Chinese: 本发明说明了一种用于制造具有使鳍与基板绝缘的绝缘层的鳍式场效应管(finFET)设备之方法。该绝缘层可防止没有该绝缘层时将流经该基板中之块状半导体材料之漏电流。可以块状半导体基板开始制造该结构，而不需要绝缘层上覆半导体基板。可以磊晶生长法形成鳍结构，因而可改善该等设备中之鳍高度的一致性。