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公开(公告)号：KR1020010010388A
公开(公告)日：2001-02-05
申请号：KR1019990029258
申请日：1999-07-20
IPC: H04L12/46
Abstract: PURPOSE: A simulation apparatus for estimating router performance is provided to estimate affect of the router performance to point to point quality by simulating at a network situation similar to a real situation. CONSTITUTION: A simulation apparatus for estimating router performance comprises a simulation control and edition part(11) which designs a virtual network and processes and parses a result after simulation. The simulation control edition and part(11) has a simulation designer(111) that is used for a virtual network simulation design and has a resource editor(113), a network design editor(114), and a network property editor(115). A simulation engine part(15) extracts network constituent element values from databases(12,13,14) to construct network simulation. A router connection configuration part(16) has a simulation time adjuster(161), a packet converter(162) and a physical connection function(163). When not using the configuration part(16), the simulation apparatus is configured so as to operate as a network simulator on a computer.
Abstract translation: 目的：提供一种用于估计路由器性能的仿真设备，以通过在类似于真实情况的网络情况下模拟来估计路由器性能对点对点质量的影响。 构成：用于估计路由器性能的仿真装置包括仿真控制和编辑部分（11），其设计虚拟网络并且在仿真之后处理和解析结果。 模拟控制版和部分（11）具有用于虚拟网络仿真设计的仿真设计器（111），并具有资源编辑器（113），网络设计编辑器（114）和网络属性编辑器（115） 。 模拟引擎部分（15）从数据库（12,13,14）中提取网络组成元素值以构建网络模拟。 路由器连接配置部分（16）具有仿真时间调整器（161），分组转换器（162）和物理连接功能（163）。 当不使用配置部分（16）时，模拟装置被配置为在计算机上作为网络模拟器操作。
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公开(公告)号：KR1019970056253A
公开(公告)日：1997-07-31
申请号：KR1019950055850
申请日：1995-12-23
Applicant: 한국전자통신연구원
IPC: H04L12/28
Abstract: 본 발명은 종래의 문제점중 서비스사용자가 망운용자에게 서비스 가입 및 관리를 요청하는 서비스를, 망운용자와 서비스사용자의 중간에서 서비스 에이전트를 두어 상호간 서비스 제공에 따른 관리를 신속하고 신뢰성있는 서비스로서 제공하는 서비스사용자와 서비스 에이전트간의 그룹화된 통신 서비스 제공 시스템 및 그 운용방법을 제공하는 데 그 목적이 있다.
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公开(公告)号：KR1019970002074B1
公开(公告)日：1997-02-21
申请号：KR1019930008512
申请日：1993-05-18
IPC: H03M13/00
Abstract: The 6 bytes shift register(21) modifies single bit error of the cell header and the 5 bytes syndrome generator(22) generates the syndrome signal of the 5 successive bytes per byte clock. The multiplexor(23) multiplexes the syndrome load and the syndrome register(24) stores the output signal temporarily, then outputs it. The exclusive OR calculus means(25) updates the syndrome signal and the syndrome decoder(28) generates the judgement signal of the syndrome calculation. The syndrome pattern decoder(27) decodes 8 syndrome pattern which single bit error generates in the first byte among 5 bytes data returning step by step. The error modifier(26) amends the error, if the error signal is single bit error, single bit error decoder sets single bit error signal to one.
Abstract translation: 6字节移位寄存器（21）修改单元头的单位错误，5字节校正子发生器（22）产生每字节时钟5个连续字节的校正子信号。 复用器（23）多路复用负载，并且校验器寄存器（24）临时存储输出信号，然后输出。 异或微积分装置（25）更新校正子信号，并且校正子解码器（28）产生校正子计算的判断信号。 综合征模式解码器（27）解码逐步返回的5字节数据中的第一个字节中产生单位错误的8个校验码模式。 错误修正器（26）修正错误，如果错误信号是单位错误，则单位错误解码器将单位错误信号设置为1。
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Patent Agency Ranking
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公开(公告)号：KR1019960003505B1
公开(公告)日：1996-03-14
申请号：KR1019920026122
申请日：1992-12-29
IPC: H04L12/28
CPC classification number: H04J3/247 , H04L2012/5651 , H04L2012/5672 , H04L2012/5679 , H04N21/23655 , H04N21/64307 , H04Q11/0478
Abstract: The ATM multiplexor receives an ATM cell and eliminates a temporary displacement of a cell. A priority encoder decides that a transfer should be performed in order from an input terminal where many waiting cells exist. A connection table process produces a conversion header. An ATM cell is produced to assemble a header for producing a complete cell by deciding a transfer order according to a service priority process order. The transfer of a payload is controlled and a clock signal is generated. The multiplexor multiplexes video data as well as telephone service, and maintains low cell loss rate.
Abstract translation: ATM多路复用器接收一个ATM信元并消除一个单元的临时位移。 优先编码器确定应当从存在许多等待单元的输入端子依次执行传送。 连接表过程产生转换头。 通过根据服务优先级处理顺序决定传送顺序，生成ATM信元以组合用于产生完整小区的报头。 控制有效载荷的传送并产生时钟信号。 复用器多路复用视频数据以及电话服务，并保持较低的信元丢失率。
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公开(公告)号：KR1019960002683B1
公开(公告)日：1996-02-24
申请号：KR1019920024194
申请日：1992-12-14
IPC: H04L12/28
Abstract: an input/output signal generator driven by a system clock supplied from a network; a video codec connector for impendence-matching an input/output signal from the input/output signal generator and a video signal upon connection of a video codec; a convergence part layer generator for generating a CS-PDU payload by processing a convergence part layer which receives the input/output signal from the input/output signal generator and data and a clock signal from the video codec connector; an SAR part layer processor for receiving an output signal from the convergence part layer generator to generate an SAR header and for connecting the header to the CS-PDU payload to transmit the connected SAR-PDU payload to an asynchronous transfer mode layer; a clock information generator for receiving the input/output signal from the input/output signal generator and the clock signal from the video codec connector and for generating acknowledging information being synchronous to a network driving clock and required for clock restoration; and a managing/state signal processor for communicating a managing/state signal in a transmitting part to an external controller.
Abstract translation: 由网络提供的系统时钟驱动的输入/输出信号发生器; 视频编解码器连接器，用于在连接视频编解码器时阻止来自输入/输出信号发生器的输入/输出信号和视频信号的匹配; 用于通过处理从输入/输出信号发生器接收输入/输出信号的会聚部分层和来自视频编解码器连接器的时钟信号来产生CS-PDU有效载荷的会聚部分层发生器; SAR部分层处理器，用于从会聚部分层发生器接收输出信号以产生SAR报头，并将标题连接到CS-PDU有效载荷，以将连接的SAR-PDU有效载荷发送到异步传输模式层; 时钟信息发生器，用于从输入/输出信号发生器接收输入/输出信号和来自视频编解码器连接器的时钟信号，并产生与网络驱动时钟同步且与时钟恢复所需的确认信息; 以及用于将发送部分中的管理/状态信号传送到外部控制器的管理/状态信号处理器。
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公开(公告)号：KR1019960002682B1
公开(公告)日：1996-02-24
申请号：KR1019920024193
申请日：1992-12-14
IPC: H04L12/28
Abstract: an input/output signal generator driven by a system clock supplied from a network and for receiving a buffer state signal and a managing signal; an SAR header checking means for receiving an input/output control signal from the input/output signal generator and receiving an SAR-PDU transmitted from an asynchronous transfer mode layer to check whether an SAR header is normal; a video information compensating means connected to the SAR header checking means, for receiving the input/output signal from the input/output signal generator to output an acknowledging bit signal and for compensating abnormal SAR-PDU ; a convergence part layer restoring means for receiving an effective SAR-PDU payload from the video information compensating means to output data and a restoring clock, to thereby restore CS-PDU; a clock restoring means for receiving the acknowledging bit from the video information restoring means and a network driving clock from the exterior and for supplying the restoring clock to the convergence part layer restoring means; a video codec connecting means for performing impendence matching and line encoding upon the application of the data and clock to a video codec; and a managing/state signal processor for communicating a managing/state signal in a transmitting part to an external controller.
Abstract translation: 由从网络提供的系统时钟驱动并用于接收缓冲状态信号和管理信号的输入/输出信号发生器; SAR报头检查装置，用于从输入/输出信号发生器接收输入/输出控制信号，并接收从异步传输模式层发送的SAR-PDU，以检查SAR报头是否正常; 连接到SAR标题检查装置的视频信息补偿装置，用于从输入/输出信号发生器接收输入/输出信号以输出确认位信号并补偿异常SAR-PDU; 会聚部分层恢复装置，用于从视频信息补偿装置接收有效的SAR-PDU有效载荷以输出数据和恢复时钟，从而恢复CS-PDU; 时钟恢复装置，用于从视频信息恢复装置接收确认位和从外部接收网络驱动时钟，并将恢复时钟提供给会聚部分层恢复装置; 视频编解码器连接装置，用于在将视频编解码器应用数据和时钟时执行阻抗匹配和行编码; 以及用于将发送部分中的管理/状态信号传送到外部控制器的管理/状态信号处理器。
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