RESOURCE ALLOCATION FOR FEEDBACK CHANNELS IN SIDELINK COMMUNICATIONS

    公开(公告)号:US20230354387A1

    公开(公告)日:2023-11-02

    申请号:US18137200

    申请日:2023-04-20

    Applicant: Apple Inc.

    CPC classification number: H04W72/40 H04L5/0016 H04L1/1812

    Abstract: Some aspects of this disclosure relate to apparatuses and methods for implementing resource allocations for feedback channels in sidelink communications. A UE can be configured to receive a physical sidelink control channel (PSCCH) transmission or a physical sidelink shared channel (PSSCH) transmission over a sidelink between the UE and a second UE for sidelink communication. The UE can allocate a set of resource elements within an interlace including multiple resource blocks to carry physical sidelink feedback channel (PSFCH) content associated with the received PSCCH transmission or PSSCH transmission, where the set of resource elements includes a first resource element in a first resource block of the interlace, and a second resource element in a second resource block of the interlace. The UE can be further configured to transmit the PSFCH content carried by the set of resource elements as a PSFCH transmission to the second UE.

    DOWNLINK (DL) AND UPLINK (UL) SCHEDULING FOR TRANSMISSION ABOVE 52.6 GHZ

    公开(公告)号:US20230239846A1

    公开(公告)日:2023-07-27

    申请号:US17439680

    申请日:2020-10-16

    Applicant: Apple Inc.

    CPC classification number: H04W72/0453 H04W72/23 H04W72/02

    Abstract: Some aspects of this disclosure relate to apparatuses and methods for implementing downlink and uplink scheduling in communication above 52.6 GHz. For example, some aspects of this disclosure relate to a base station. The base station includes a transceiver configured to communicate over a wireless network with a user equipment (UE) and a processor communicatively coupled to the transceiver. The processor determines that the communication between the base station and the UE is in a frequency range above 52.6 GHz. In response to the determination, the processor disables a frequency main resource assignment (FDRA), modifies a Resource Block Group (RBG) size, or modifies a Resource Indication Value (RIV) determination. The processor generates a Downlink Channel Indicator (DCI) based at least on one or more of the disabled FDRA, the modified RBG size, or the modified RIV determination. The processor transmits, using the transceiver, the DCI to the UE.

Patent Agency Ranking