-
公开(公告)号：JP2001043674A
公开(公告)日：2001-02-16
申请号：JP21730899
申请日：1999-07-30
Applicant: FUJITSU LTD
Inventor： HOSOI TOSHIO , OGAWA JUNJI
IPC: G11C11/401 , G11C11/407 , G11C11/409 , H01L21/8242 , H01L27/108
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory in which a DRAM itself has plural ports, plural addresses can be accessed simultaneously, and enlarging of wafer area can be evaded. SOLUTION: Memory blocks B11-B41 are commonly connected to a common wiring JB1, memory blocks B12-B42 are commonly connected to a common wiring JB2, memory blocks B13-B43 are commonly connected to a common wiring JB3, and memory blocks B14-B44 are commonly connected to a common wiring JB4. When ports P1, P2 access memory blocks connected to common wiring being different, simultaneous access can be performed by controlling switches S11-S14 and S21-S22. When ports P1, P2 access memory blocks connected to common wiring being same, after accessing of a port previously starting to access is finished, accessing of the other port is started. It can be performed in also a semiconductor memory having three ports or more.
-
公开(公告)号：JPH113587A
公开(公告)日：1999-01-06
申请号：JP15542997
申请日：1997-06-12
Applicant: FUJITSU LTD
Inventor： GOTO KOTARO , TAMURA HIROTAKA , OGAWA JUNJI
IPC: G11C11/407
Abstract: PROBLEM TO BE SOLVED: To make it unnecessary to consider dispersion in the manufacturing process and the variation of power source voltage in timing design, to reduce the period of timing design and to curtail manufacturing cost by digitalizing timing adjustment with an integer times of the delay stages of the first to n-th clock generating circuits. SOLUTION: A multi-phase clock generating circuit 26 delays a clock CLKi through 2 m, 4 m, 6 m-2 nm inverters and generates clocks ϕ1 to ϕn whose phases are formed by shifting the phase of the clock CLKi by θ to nθ where m is a natural number. A timing adjusting circuit 22 determines the timings of the activated point and inactivated point of the control signal CNT by counting the clocks ϕ1 to ϕn generated by the generating circuit 26 to supply the timing control signal CNT to a DRAM core 3 through a timing buffer circuit 27. Thus timing adjustment is digitalized with an integral multiple of the delay stage in the generating circuit 26.
-
公开(公告)号：JPH0612615B2
公开(公告)日：1994-02-16
申请号：JP949387
申请日：1987-01-19
Applicant: FUJITSU LTD
Inventor： OGAWA JUNJI
IPC: G11C11/41 , G06F12/02 , G06F12/04 , G11C11/34 , G11C11/401
-
公开(公告)号：JPH0582703A
公开(公告)日：1993-04-02
申请号：JP24104591
申请日：1991-09-20
Applicant: FUJITSU LTD
Inventor： OGAWA JUNJI , TAKITA MASAHITO
IPC: H01L21/82 , H01L21/822 , H01L23/495 , H01L23/50 , H01L27/04
Abstract: PURPOSE:To minimize an parasitic impedance of a signal route which starts from a bonding pad only when a signal is output or when a signal is input/ output and reaches an outer lead, reduce the generation of noise and speed up read-out when a plurality of output buffers are switched on simultaneously, shorten the signal route and speed up the performance. CONSTITUTION:A bonding pad 25 formed only when a signal is output or when a signal is output/input, is formed in the peripheral part of a device formation plane 23 out of the bonding pads while an inner lead 27 where only a signal is output or a signal is output/input, is arranged to correspond to the bonding pad 25 where only a signal is output or a signal is output/input. Their tip is positioned above the peripheral part of the device formation plane 23.
-
公开(公告)号：JPH0355659A
公开(公告)日：1991-03-11
申请号：JP19203689
申请日：1989-07-25
Applicant: FUJITSU LTD
Inventor： OGAWA JUNJI
Abstract: PURPOSE:To omit the non-ignition arithmetic operations and to increase the processing speed of a semiconductor information processor by outputting the decoding signal of only connection after deciding an output signal of a neuron of the preceding layer, extracting a store address signal, and at the same time reading out the weight value. CONSTITUTION:An output signal xi received from a neuron of the preceding layer undergoes the decision of its state via a state deciding means 1. This deciding result is outputted as + or -SDEC, where (+) and (-) mean the excitement and the suppression respectively. The result of non-ignition (0) is neglected. Then the addresses A1 - A256 are partly extracted in accordance with the signal + or -SDEC. These extracted addresses are successively stored in the FIFO 4a and 5a. Meanwhile the addresses Ai extracted at the sides A0 and B0 are successively selected toward B from A by a selection means 6. Thus the weight value Wij equivalent to the corresponding number of addresses are successively read out of a storage means 7. A state signal generating means 8 outputs the state signals corresponding to the address holding means 4 and 5 selected by the means 6. Then an arithmetic means 9 performs a product sum arithmetic operation based on + or -1 and the value Wij and outputs this arithmetic result yi.
-
Patent Agency Ranking
公开(公告)号：JPH02236659A
公开(公告)日：1990-09-19
申请号：JP5749489
申请日：1989-03-09
Applicant: FUJITSU LTD
Inventor： OGAWA JUNJI
Abstract: PURPOSE:To load a large number of neurons on a chip by providing a multiplier, an adder for a multiplication result, and a comparator to convert an addition result of one neuron to ternary values with a threshold value. CONSTITUTION:The output of a neuron chip i.e. input (input/output of every layer) is set at the one with ternary values of + or -1 and 0, and is expressed in two bits So0, Soi1, Si0, and Si1. Therefore, the multiplier 22 passes weight Wij read out from a cell array as it is or after inverting according to the +1, -1, or 0 or the input Si0 and Si1, or sets it at 0. Also, a threshold value processing circuit 26 checks the output of the adder 24 with two threshold values and sets is at +1, 0, or -1 corresponding to high, medium, or low. Thereby, it is possible to remarkably increase the number of neurons.
-
公开(公告)号：JPH0222479B2
公开(公告)日：1990-05-18
申请号：JP5550184
申请日：1984-03-23
Applicant: FUJITSU LTD
Inventor： TAKEMAE YOSHIHIRO , NAKANO TOMIO , TATEMATSU TAKEO , TSUGE NORIHISA , OGAWA JUNJI , HORII TAKASHI , FUJII YASUHIRO , NAKANO MASAO
Abstract: A semiconductor integrated circuit device connected between first and second voltage feet lines includes an information storing circuit (3) having a fuse (F) for storing information by blowing or not blowing the fuse, a voltage level conversion circuit (10) outputting a voltage (V min cc) lower than a voltage (Vcc) between the first and second voltage feed lines to the information storing circuit, and a circuit (5) connected between the first and second voltage feed lines, for outputting a detection signal (Si) in response to a voltage value at the fuse which is varied with the blown or unblown state of the fuse. The output voltage (V min cc) from the voltage level conversion circuit (10) is set as low as possible to restrain electromigration caused at the vicinity of the blown portion of the fuse, but higher than the threshold voltage of the information detection circuit (5). Said output voltage (V min cc) is at a predetermined value when the voltage between the first and second voltage feed lines is within a predetermined range, and increases in response to the increment of the voltage between the first and second voltage feed lines when said last mentioned voltage exceeds a predetermined range.
-
公开(公告)号：JPS63142593A
公开(公告)日：1988-06-14
申请号：JP28968086
申请日：1986-12-04
Applicant: FUJITSU LTD
Inventor： OGAWA JUNJI , KOBAYASHI KAZUYA
IPC: G11C11/401 , G11C11/34 , G11C11/407
Abstract: PURPOSE:To obtain a memory suitable for picture processing by providing a pre-decoder of each selected dimension so as to output plural bits of designated dimension at the same time. CONSTITUTION:Pre-decoders 18x, 18y, 18s decode a segment comprising m-bit at the designated dimension among n-bit on each word line while receiving multi-dimension control signals x, y, s and segment addresses B0-, the inverse of B3. The decoded output turns on/off corresponding transfer gates 72x, 72y, 72s via m-set of exclusive selection lines 30x, 30y, 30s of a multi-dimension selection circuit 16. Thus, outputs of sense amplifiers SA72, SA73 or the like are led to the m-set of data buses 20 having a prescribed relation with the selection lines. Thus, the plural bits of the designated dimension are read at the same time and the memory is suitable for picture processing or the like.
-
公开(公告)号：JPS6322399B2
公开(公告)日：1988-05-11
申请号：JP20986083
申请日：1983-11-10
Applicant: FUJITSU LTD
Inventor： TAKEMAE YOSHIHIRO , TSUGE NORIHISA , OGAWA JUNJI , FUJII YASUHIRO , NAKANO TOMIO , TATEMATSU TAKEO , HORII TAKASHI , NAKANO MASAO
-
公开(公告)号：JP2010035186A
公开(公告)日：2010-02-12
申请号：JP2009213258
申请日：2009-09-15
Applicant: Fujitsu Ltd , Keio Gijuku , 学校法人慶應義塾 , 富士通株式会社
Inventor： TAMURA YASUTAKA , CHEUNG TSU-SHING , YAMAZAKI DAISUKE , OGAWA JUNJI , OKANIWA TAKESUKE
Abstract: PROBLEM TO BE SOLVED: To provide a signal processing circuit (comparator circuit) capable of receiving signals without code interference for high-speed signals. SOLUTION: Provided is the signal processing circuit which includes: an input circuit (3111) which processes an input signal and outputs an output signal in such a way that a property of signal transfer from the input signal to the output signal is varied by a clock signal; and an amplifier circuit (3102) for amplifying the output signal of the input circuit during a period of time in which it is brought into active state by the clock signal. COPYRIGHT: (C)2010,JPO&INPIT
Abstract translation: 要解决的问题：提供能够接收高速信号无代码干扰的信号的信号处理电路（比较器电路）。 解决方案：提供了信号处理电路，其包括：输入电路（3111），其处理输入信号并输出输出信号，使得从输入信号到输出信号的信号传送的特性变化 通过时钟信号; 以及放大器电路（3102），用于在通过时钟信号进入激活状态的时间段期间放大输入电路的输出信号。 版权所有（C）2010，JPO＆INPIT
-
-
-
-
-
-
-
-
-
Search Results
115
records
(took 0.029 seconds)
