Abstract:
A circuit comprising an input, a ground, a first switch, a second switch and a bi-polar memristor, wherein the first switch is a first transistor and a gate of the first transistor is connected to a line to instruct setting of the bi-polar memristor, and the second switch is a second transistor and a gate of the second transistor is connected to a line to instruct re-setting of the bi-polar memristor.
Abstract:
A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.
Abstract:
A printhead with a number of memristor cells and a number of firing cells coupled to a shared fire line is described. The printhead includes a number of firing cells to deposit an amount of fluid onto a print medium. Each firing cell includes a firing chamber to hold the amount of fluid, an opening to dispense the amount of fluid onto the print medium, and an ejector to eject the amount of fluid through the opening. The printhead also includes a number of memristor cells to store information, a multiplexing circuit to select at least one memristor cell and at least one firing cell based on at least one control signal, and a shared fire line to activate the selected memristor cell and the selected firing cell.
Abstract:
A memory controller includes a voltage control module that operates to isolate a target memristor of a memory crossbar array. The voltage control module applies a column voltage to a column line coupled to the target memristor, applies a first row voltage to all row lines not coupled to the target memristor and a second row voltage to a row line coupled to the target memristor, and senses a current through the target memristor to determine a state of the target memristor. The memory crossbar array includes a plurality of column lines, a plurality of row lines, a plurality of memristors, and a plurality of shorting switches. Each memristor is coupled between a unique combination of one column line and one row line. Each shorting switch has a high impedance resistor and a low impedance transistor, and each shorting switch is coupled to an end of a unique row line.
Abstract:
A printhead with an off-chip memristor assembly is described. The printhead includes a nozzle, a firing chamber to hold an amount of fluid, and an ejector to eject the amount of fluid through the nozzle. The printhead also includes an off-chip memristor assembly. The off-chip memristor assembly includes a bottom electrode. A number of switching oxides extend from the bottom electrode. A number of top electrodes extend from the number of switching oxides to align with a number of bonding pads on an integrated circuit. A portion of the bottom electrode, a switching oxide and a top electrode form a memristor device. The bottom electrode is a common ground for a number of memristor devices.
Abstract:
Ink property sensing on a printhead is described. In an example, a substrate for a printhead includes a cap layer having bores. Chambers are formed beneath the cap layer in fluidic communication with the bores. Fluid ejectors are disposed in at least a portion of the chambers. At least one ion-sensitive field effect transistor (ISFET) is disposed in a respective at least one of the chambers. An electrode is disposed in each of the chambers having an ISFET and capacitively coupled to said ISFET through a dielectric.
Abstract:
A non-volatile memory element with thermal-assisted switching control is disclosed. The non-volatile memory element is disposed on a thermal inkjet resistor. Methods for manufacturing the combination and methods of using the combination are also disclosed.
Abstract:
A resistive memory element is provided, having a bottom electrode, a top electrode, and an active region sandwiched therebetween. The resistance memory element has a V-shape. Methods of manufacturing the V-shape resistive memory element and crossbar structures employing the V-shape resistive memory element are also provided.
Abstract:
Devices to detect a substance and methods of producing such a device are disclosed. An example device to detect a substance includes a housing defining a first chamber and a substrate coupled to the housing. The substrate includes nanostructures positioned within the first chamber. The nanostructures are to react to the substance when exposed thereto. The device includes a first heater positioned within the first chamber. The heater is to heat at least a portion of the substance to ready the device for analysis.
Abstract:
An annealing device may include an array of thermal heaters, each thermal heater comprising a resistive element formed into a cavity and wherein each of the thermal heaters within the array of thermal heaters are selectively activated to anneal an annealable material deposited into the cavities.