公开(公告)号：US09424034B2

公开(公告)日：2016-08-23

申请号：US13931008

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Glenn Hinton ,  Bret Toll ,  Ronak Singhal

IPC: G06F9/04 ,  G06F9/30

CPC classification number: G11C7/1036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30163

Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.

Abstract translation: 处理器包括N位寄存器和用于接收多寄存器存储器访问指令的解码单元。 多寄存器存储器访问指令是指示存储器位置和寄存器。 处理器包括与解码单元和N位寄存器耦合的存储器存取单元。 存储器访问单元响应于多个寄存器存储器访问指令执行多个寄存器存储器存取操作。 该操作涉及在包括指定的寄存器的每个N位寄存器中涉及N位数据。 该操作还涉及对应于所指示的存储器位置的M×N位存储器线的不同对应的N位部分。 要在多个寄存器存储器访问操作中涉及的N位寄存器中的N位数据的总位数至少等于存储器行的M×N位的至少一半。

公开(公告)号：US09367325B2

公开(公告)日：2016-06-14

申请号：US13931887

申请日：2013-06-29

Applicant: Intel Corporation

Inventor： Bret Toll ,  Jason W. Brandt ,  John Holm

IPC: G06F13/00 ,  G06F15/00 ,  G06F9/38

CPC classification number: G06F9/3009 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/46 ,  G06F15/80

Abstract: A method is described that includes deciding to migrate a thread from a first processing core to a second processing core. The method also includes automatically in hardware migrating first context of the thread of the first processing core whose register definition is also found on the second processing core to the second processing core. The method also includes automatically in hardware migrating second context of the thread of the first processing core whose register definition is not found on the second processing core to a first storage location external to the second processing core. The message also includes automatically in hardware migrating third context of the thread from a second storage location external to the second processing core to register definition found on the second processing core but not found on the first processing core.

Abstract translation: 描述了一种方法，其包括决定将线程从第一处理核心迁移到第二处理核心。 该方法还自动地将第一处理核心的线程的第一上下文自动迁移到其第二处理核心的第二处理核心上也将其寄存器定义也被发现。 该方法还自动地将在第二处理核心上没有发现其寄存器定义的第一处理核心的线程的第二上下文迁移到第二处理核心外部的第一存储位置。 消息还自动地包括将线程的第三上下文从第二处理核心外部的第二存储位置迁移到在第二处理核心上找到但在第一处理核心上找不到的寄存器定义的硬件。