公开(公告)号：US10831625B2

公开(公告)日：2020-11-10

申请号：US16080234

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Yao Zu Dong ,  Kun Tian

IPC: G06F11/00 ,  G06F11/22 ,  G06F11/14 ,  G06F11/30 ,  G06F11/34

Abstract: An apparatus and method performing debug and rollback operations using snapshots. For example, one embodiment of an apparatus comprises: a graphics processing unit (GPU) to perform graphics processing operations by executing graphics commands; a command parser to parse graphics commands submitted to the GPU and generate a list of graphics memory pages which will be affected by the graphics commands; an I/O state tracker to track I/O accesses from a graphics driver to determine a list of registers affected by the I/O accesses; snapshot circuitry and/or logic to perform a memory snapshot and I/O snapshot based on the list of graphics memory pages and the list of registers, respectively; and rollback circuitry and/or logic to perform a rollback operation using the memory snapshot and I/O snapshot in response to detecting a GPU error condition.

公开(公告)号：US10769078B2

公开(公告)日：2020-09-08

申请号：US16453995

申请日：2019-06-26

Applicant: Intel Corporation

Inventor： Niranjan L. Cooray ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran ,  Satyeshwar Singh ,  Sameer Kp ,  Ankur N. Shah ,  Kun Tian

IPC: G06F12/109 ,  G06F11/07 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/0802 ,  G06F13/40

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：US10565676B2

公开(公告)日：2020-02-18

申请号：US15488547

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Adam T. Lake ,  Guei-Yuan Lueh ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Altug Koker ,  Subramaniam M. Maiyuran ,  Eric C. Samson ,  David J. Cowperthwaite ,  Zhi Wang ,  Kun Tian ,  David Puffer ,  Brian T. Lewis

IPC: G06T1/20 ,  G06T1/60

Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.

公开(公告)号：US20180308209A1

公开(公告)日：2018-10-25

申请号：US16010692

申请日：2018-06-18

Applicant: Intel Corporation

Inventor： Murali Ramadoss ,  Balaji Vembu ,  Eric C. Samson ,  Kun Tian ,  David J. Cowperthwaite ,  Altug Koker ,  Zhi Wang ,  Joydeep Ray ,  Subramaniam M. Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/50

Abstract: Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for an apparatus comprising a thread dispatcher to dispatch a thread for execution; a compute unit having a single instruction, multiple thread architecture, the compute unit to execute multiple concurrent threads; and a memory coupled with the compute unit, the memory to store thread state for a suspended thread, wherein the compute unit is to: detect that all threads on the compute unit are blocked from execution, select a victim thread from the multiple concurrent threads, suspend the victim thread, store thread state of the victim thread to the memory, and replace the victim thread with an additional thread to be executed.

公开(公告)号：US10043232B1

公开(公告)日：2018-08-07

申请号：US15482809

申请日：2017-04-09

Applicant: Intel Corporation

Inventor： Murali Ramadoss ,  Balaji Vembu ,  Eric C. Samson ,  Kun Tian ,  David J. Cowperthwaite ,  Altug Koker ,  Zhi Wang ,  Joydeep Ray ,  Subramaniam M. Maiyuran ,  Abhishek R. Appu

IPC: G06F9/50 ,  G06F9/48 ,  G06T1/20

Abstract: One embodiment provides for a general-purpose graphics processing unit comprising a compute cluster including multiple compute units, a stall notification module to detect that one or more compute units in the compute cluster are stalled and send stall notification, and a rebalance module to receive the stall notification, the rebalance module to migrate a first workload from one or more stalled compute units in response to the stall notification.

公开(公告)号：US09921868B2

公开(公告)日：2018-03-20

申请号：US14930413

申请日：2015-11-02

Applicant: Intel Corporation

Inventor： Yao Zu Dong ,  Yunhong Jiang ,  Kun Tian

IPC: G06F13/24 ,  G06F9/455 ,  G06F9/48 ,  H04L29/08 ,  G06F9/50

CPC classification number: G06F9/45558 ,  G06F9/45545 ,  G06F9/48 ,  G06F9/4812 ,  G06F9/5077 ,  G06F13/24 ,  G06F2009/45595 ,  G06F2213/2408 ,  H04L69/321

Abstract: Generally, this disclosure describes systems (and methods) of moderating interrupts in a virtualization environment. An overflow interval is defined. The overflow interrupt interval is used to trigger activation of an inactive guest so that the guest may respond to a critical event. The guest, including a network application, may be active for a first time interval and inactive for a second time interval. A latency interrupt interval may be defined. The latency interrupt interval is configured for interrupt moderation when the network application associated with a packet flow is active, i.e., when the guest including the network application is active on a processor. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

公开(公告)号：US09824026B2

公开(公告)日：2017-11-21

申请号：US14780401

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Yao Zu Dong ,  Kun Tian

IPC: G06F9/45 ,  G06F12/08 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/109 ,  G06F12/02 ,  G06F9/455 ,  G06F9/50 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F12/109 ,  G06F9/455 ,  G06F9/45533 ,  G06F9/45558 ,  G06F9/50 ,  G06F12/02 ,  G06F2009/45583 ,  G06F2212/657 ,  G06T1/20 ,  G06T1/60 ,  G06T2200/28

Abstract: An apparatus and method are described for managing a virtual graphics processor unit (GPU). For example, one embodiment of an apparatus comprises: a dynamic addressing module to map portions of an address space required by the virtual machine to matching free address spaces of a host if such matching free address spaces are available, and to select non-matching address spaces for those portions of the address space required by the virtual machine which cannot be matched with free address spaces of the host; and a balloon module to perform address space ballooning (ASB) techniques for those portions of the address space required by the virtual machine which have been mapped to matching address spaces of the host; and address remapping logic to perform address remapping techniques for those portions of the address space required by the virtual machine which have not been mapped to matching address spaces of the host.

公开(公告)号：US09448831B2

公开(公告)日：2016-09-20

申请号：US14125148

申请日：2013-07-01

Applicant: INTEL CORPORATION

Inventor： Yaozu Dong ,  Kun Tian ,  Ke Yu

IPC: G06F9/455 ,  G06F12/08 ,  G06F9/50 ,  G06T1/60

CPC classification number: G06F9/45558 ,  G06F9/455 ,  G06F9/45533 ,  G06F9/5077 ,  G06F12/08 ,  G06F2009/45583 ,  G06T1/60

Abstract: Systems and methods may provide for identifying an assigned address space of a virtual machine (VM), wherein the assigned address space is associated with a graphics memory. Additionally, the assigned address space may be ballooned to disable usage by the VM of a remaining address space in the graphics memory that is not assigned to the VM. In one example, a view of the assigned address space by the VM may be identical to a view of the assigned address space by a virtual machine monitor (VMM) associated with the VM.

Abstract translation: 系统和方法可以提供用于识别虚拟机（VM）的分配的地址空间，其中所分配的地址空间与图形存储器相关联。 此外，分配的地址空间可以被气球化以禁止虚拟机使用未分配给VM的图形存储器中的剩余地址空间。 在一个示例中，VM分配的地址空间的视图可以与由VM关联的虚拟机监视器（VMM）分配的地址空间的视图相同。

公开(公告)号：US09336040B2

公开(公告)日：2016-05-10

申请号：US14486270

申请日：2014-09-15

Applicant: Intel Corporation

Inventor： Yao Zu Dong ,  Kun Tian

IPC: G06F9/455 ,  H04L29/08 ,  G06F9/54 ,  G06F9/44

CPC classification number: H04L67/148 ,  G06F9/451 ,  G06F9/45533 ,  G06F9/45558 ,  G06F9/466 ,  G06F9/541 ,  G06F11/3612 ,  G06F2009/4557 ,  H04L67/10 ,  H04L69/16

Abstract: Examples may include a remapping of sessions for a multi-threaded application that may be executed at a server or a client coupled to the server via a plurality of transmit control protocol (TCP) connections. Sessions may be remapped such that the multi-threaded application may expect to route sessions through a same TCP connection but the sessions are actually outputted via separate TCP connections.

Abstract translation: 示例可以包括可以在经由多个传输控制协议（TCP）连接耦合到服务器的服务器或客户机上执行的多线程应用的会话的重新映射。 会话可以被重新映射，使得多线程应用可能期望通过相同的TCP连接路由会话，但是会话实际上是通过单独的TCP连接输出的。

公开(公告)号：US09098337B2

公开(公告)日：2015-08-04

申请号：US13675669

申请日：2012-11-13

Applicant: Intel Corporation

Inventor： Yao Zu Dong ,  Kun Tian

IPC: G06F9/455 ,  G06F9/46 ,  G06F9/50

CPC classification number: G06F9/5033 ,  G06F9/45558 ,  G06F2009/45562

Abstract: Embodiments of apparatus, computer-implemented methods, systems, and computer-readable media are described herein for a virtual machine monitor. The virtual machine monitor may be configured to determine whether to schedule a virtual central processing unit of one of a plurality of virtual machines on a first physical processing unit of a plurality of physical processing units. Each virtual machine may have one or more virtual central processing units. The determination may be based at least in part on whether a context of the virtual central processing unit suggests a desired cache hit rate on one or more cache units of the apparatus by the first physical processing unit when operating the virtual central processing unit.

Abstract translation: 这里描述了用于虚拟机监视器的装置，计算机实现的方法，系统和计算机可读介质的实施例。 虚拟机监视器可以被配置为确定是否在多个物理处理单元的第一物理处理单元上调度多个虚拟机之一的虚拟中央处理单元。 每个虚拟机可以具有一个或多个虚拟中央处理单元。 该确定可以至少部分地基于在操作虚拟中央处理单元时虚拟中央处理单元的上下文是否由第一物理处理单元在设备的一个或多个高速缓存单元上建议期望的高速缓存命中率。