公开(公告)号：US10417135B2

公开(公告)日：2019-09-17

申请号：US15718071

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Zhe Wang ,  Zeshan A. Chishti ,  Alaa R. Alameldeen ,  Rajat Agarwal

IPC: G06F12/08 ,  G06F12/12 ,  G06F12/10 ,  G06F12/0877 ,  G06F12/0862 ,  G06F12/128 ,  G06F12/0888 ,  G06F12/1009 ,  G06F12/0817

Abstract: Systems, apparatuses and methods may provide for technology to maintain a prediction table that tracks missed page addresses with respect to a first memory. If an access request does not correspond to any valid page addresses in the prediction table, the access request may be sent to the first memory. If the access request corresponds to a valid page address in the prediction table, the access request may be sent to the first memory and a second memory in parallel, wherein the first memory is associated with a shorter access time than the second memory.

公开(公告)号：US10402336B2

公开(公告)日：2019-09-03

申请号：US15475244

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Berkin Akin ,  Rajat Agarwal ,  Jong Soo Park ,  Christopher J. Hughes

IPC: G06F12/08 ,  G06F12/0888 ,  G06F12/0811 ,  G06F12/0831

Abstract: In one embodiment, a processor includes: a core including a decode unit to decode a memory access instruction having a no-locality hint to indicate that data associated with the memory access instruction has at least one of non-spatial locality and non-temporal locality; and a locality controller to determine whether to override the no-locality hint based at least in part on one or more performance monitoring values. Other embodiments are described and claimed.

公开(公告)号：US20190258583A1

公开(公告)日：2019-08-22

申请号：US16402734

申请日：2019-05-03

Applicant: Intel Corporation

Inventor： Suresh S. Chittor ,  Rajat Agarwal ,  Wei P. Chen

IPC: G06F12/0893

Abstract: An embodiment of a memory controller device includes technology to control access to a multi-level memory including at least a first level memory and a second level memory, provide direct access to the first level memory based on a system memory address, cache accesses to the second level memory in a second portion of the first level memory, and address a memory space with a total memory capacity which includes a first capacity of the first portion of the first level memory plus a second capacity of the second level memory. Other embodiments are disclosed and claimed.

公开(公告)号：US10275001B2

公开(公告)日：2019-04-30

申请号：US14752512

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Timothy Y. Kam ,  Sandeep Ahuja ,  Rajat Agarwal ,  Avinash Sodani ,  Jinho Suh ,  Meenakshisundaram Chinthamani

IPC: G06F1/20 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3225

Abstract: Disclosed herein is a computing device configured to implement thermal throttling of a component of the computing device. The computing device includes an electronic component and a temperature sensor thermally coupled to the electronic component. The computing device also includes a thermal management controller to receive a temperature measurement from the temperature sensor and generate a throttling factor for the electronic component. If the temperature measurement is greater than a specified threshold, the throttling factor is to reduce performance of the electronic component to be at least the performance guarantee for the electronic component.

公开(公告)号：US10241912B2

公开(公告)日：2019-03-26

申请号：US15457847

申请日：2017-03-13

Applicant: Intel Corporation

Inventor： Raj K. Ramanujan ,  Rajat Agarwal ,  Kai Cheng ,  Taarinya Polepeddi ,  Camille C. Raad ,  David J. Zimmerman ,  Muthukumar P. Swaminathan ,  Dimitrios Ziakas ,  Mohan J. Kumar ,  Bassam N. Coury ,  Glenn J. Hinton

IPC: G06F13/12 ,  G06F13/38 ,  G06F12/0811 ,  G06F12/0897 ,  G11C11/406 ,  G11C14/00 ,  G06F12/0895

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”

公开(公告)号：US10198354B2

公开(公告)日：2019-02-05

申请号：US15465513

申请日：2017-03-21

Applicant: INTEL CORPORATION

Inventor： Wei Chen ,  Rajat Agarwal ,  Jing Ling ,  Daniel W. Liu

IPC: G06F12/06 ,  G06F12/08 ,  G06F3/06 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/0868

Abstract: Provided are an apparatus, system, and method to flush modified data from a first memory to a persistent second memory. A first memory controller coupled to the first memory includes at least one RAS controller to read a range of addresses in the first memory. In response to receiving a command from the power control unit, the at least one RAS controller is invoked to read data from at least one range of addresses specified for the RAS controller from the first memory. A second memory controller transfers data read from the first memory determined to be modified to the second memory. The first memory controller sends a signal to the power control unit to indicate that the modified data in the range of addresses specified for the RAS controller was flushed to the second memory in response to the RAS controller completing reading the range of addresses.

公开(公告)号：US20180285279A1

公开(公告)日：2018-10-04

申请号：US15475244

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Berkin Akin ,  Rajat Agarwal ,  Jong Soo Park ,  Christopher J. Hughes

IPC: G06F12/0888 ,  G06F12/0831 ,  G06F12/0811

CPC classification number: G06F12/0888 ,  G06F12/0811 ,  G06F12/0831 ,  G06F2212/283 ,  G06F2212/6046 ,  G06F2212/621

Abstract: In one embodiment, a processor includes: a core including a decode unit to decode a memory access instruction having a no-locality hint to indicate that data associated with the memory access instruction has at least one of non-spatial locality and non-temporal locality; and a locality controller to determine whether to override the no-locality hint based at least in part on one or more performance monitoring values. Other embodiments are described and claimed.

公开(公告)号：US09910728B2

公开(公告)日：2018-03-06

申请号：US14757905

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： Debaleena Das ,  Rajat Agarwal ,  Brian S. Morris

IPC: G06F11/00 ,  G06F11/07 ,  G06F3/06

CPC classification number: G06F11/0793 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/1064

Abstract: Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having write data for locations in one of the cache lines, the write data for a location in the cache line having an error is written to an entry in a sparing directory including an address of the cache line.

公开(公告)号：US20170255561A1

公开(公告)日：2017-09-07

申请号：US15062824

申请日：2016-03-07

Applicant: Intel Corporation

Inventor： Alaa R. Alameldeen ,  Rajat Agarwal

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F12/0868 ,  G06F2212/401

Abstract: Technologies for increasing associativity of a direct mapped cache using compression include an apparatus that includes a memory to store data blocks, a cache to store a subset of the data blocks in various of physical cache blocks, and a memory management unit (MMU). The MMU is to compress data blocks associated with locations of the main memory that are mapped to a physical cache block and write the compressed data blocks to the physical cache block if the combined size of the compressed blocks satisfies a threshold size. Other embodiments are also described and claimed.

公开(公告)号：US20160378149A1

公开(公告)日：2016-12-29

申请号：US14752512

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： Timothy Y. Kam ,  Sandeep Ahuja ,  Rajat Agarwal ,  Avinash Sodani ,  Jinho Suh ,  Meenakshisundaram Chinthamani

IPC: G06F1/20 ,  G06F1/32

CPC classification number: G06F1/206 ,  G06F1/3206 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3275 ,  G06F2212/1028 ,  G11C7/04 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/16

Abstract: Disclosed herein is a computing device configured to implement thermal throttling of a component of the computing device. The computing device includes an electronic component and a temperature sensor thermally coupled to the electronic component. The computing device also includes a thermal management controller to receive a temperature measurement from the temperature sensor and generate a throttling factor for the electronic component. If the temperature measurement is greater than a specified threshold, the throttling factor is to reduce performance of the electronic component to be at least the performance guarantee for the electronic component.

Abstract translation: 这里公开了一种被配置为实现计算设备的部件的热调节的计算设备。 计算设备包括热耦合到电子部件的电子部件和温度传感器。 计算设备还包括热管理控制器，用于从温度传感器接收温度测量并产生电子部件的节流因子。 如果温度测量值大于指定的阈值，则节流因素是将电子元件的性能降至至少为电子元件的性能保证。